| /third_party/ffmpeg/libavcodec/aarch64/ |
| H A D | vp8dsp_neon.S | 344 sqsub v20.16b, v2.16b, v5.16b // clamp(PS1-QS1)
382 sqsub v4.16b, v4.16b, v19.16b // QS0 = clamp(QS0-c1)
397 sqsub v4.16b, v4.16b, v19.16b // QS0 = clamp(QS0-c1)
403 sqsub v5.16b, v5.16b, v19.16b // QS1 = clamp(QS1-c3)
414 sqsub v4.16b, v4.16b, v19.16b // QS0 = clamp(QS0-c1)
445 sqsub v6.16b, v6.16b, v16.16b // QS2 = clamp(QS2-a)
447 sqsub v5.16b, v5.16b, v19.16b // QS1 = clamp(QS1-a)
449 sqsub v4.16b, v4.16b, v22.16b // QS0 = clamp(QS0-a)
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| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 1696 __ sqsub(b19, b29, b11); in GenerateTestSequenceNEON()
1697 __ sqsub(d21, d31, d6); in GenerateTestSequenceNEON()
1698 __ sqsub(h18, h10, h19); in GenerateTestSequenceNEON()
1699 __ sqsub(s6, s5, s0); in GenerateTestSequenceNEON()
1700 __ sqsub(v21.V16B(), v22.V16B(), v0.V16B()); in GenerateTestSequenceNEON()
1701 __ sqsub(v22.V2D(), v10.V2D(), v17.V2D()); in GenerateTestSequenceNEON()
1702 __ sqsub(v8.V2S(), v21.V2S(), v2.V2S()); in GenerateTestSequenceNEON()
1703 __ sqsub(v18.V4H(), v25.V4H(), v27.V4H()); in GenerateTestSequenceNEON()
1704 __ sqsub(v13.V4S(), v3.V4S(), v6.V4S()); in GenerateTestSequenceNEON()
1705 __ sqsub(v2 in GenerateTestSequenceNEON()
[all...] |
| H A D | test-cpu-features-aarch64.cc | 1906 TEST_NEON(sqsub_0, sqsub(v0.V8B(), v1.V8B(), v2.V8B()))
1907 TEST_NEON(sqsub_1, sqsub(v0.V16B(), v1.V16B(), v2.V16B()))
1908 TEST_NEON(sqsub_2, sqsub(v0.V4H(), v1.V4H(), v2.V4H()))
1909 TEST_NEON(sqsub_3, sqsub(v0.V8H(), v1.V8H(), v2.V8H()))
1910 TEST_NEON(sqsub_4, sqsub(v0.V2S(), v1.V2S(), v2.V2S()))
1911 TEST_NEON(sqsub_5, sqsub(v0.V4S(), v1.V4S(), v2.V4S()))
1912 TEST_NEON(sqsub_6, sqsub(v0.V2D(), v1.V2D(), v2.V2D()))
1913 TEST_NEON(sqsub_7, sqsub(b0, b1, b2))
1914 TEST_NEON(sqsub_8, sqsub(h0, h1, h2))
1915 TEST_NEON(sqsub_9, sqsub(s
[all...] |
| H A D | test-disasm-sve-aarch64.cc | 2200 COMPARE(sqsub(z1.VnB(), z10.VnB(), z0.VnB()), "sqsub z1.b, z10.b, z0.b"); in TEST()
2201 COMPARE(sqsub(z2.VnH(), z11.VnH(), z1.VnH()), "sqsub z2.h, z11.h, z1.h"); in TEST()
2202 COMPARE(sqsub(z3.VnS(), z12.VnS(), z2.VnS()), "sqsub z3.s, z12.s, z2.s"); in TEST()
2203 COMPARE(sqsub(z4.VnD(), z13.VnD(), z3.VnD()), "sqsub z4.d, z13.d, z3.d"); in TEST()
3107 COMPARE(sqsub(z31.VnB(), z31.VnB(), 132), "sqsub z3 in TEST()
[all...] |
| H A D | test-api-movprfx-aarch64.cc | 1203 __ sqsub(z17.VnB(), z17.VnB(), 42); in TEST()
1597 __ sqsub(z31.VnB(), z31.VnB(), 42); in TEST()
2259 __ sqsub(z16.VnB(), p7.Merging(), z16.VnB(), z22.VnB()); in TEST()
3443 __ sqsub(z16.VnB(), p7.Merging(), z16.VnB(), z16.VnB()); in TEST()
3637 __ sqsub(z16.VnB(), p7.Merging(), z16.VnB(), z22.VnB()); in TEST()
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| H A D | test-simulator-aarch64.cc | 4602 DEFINE_TEST_NEON_3SAME(sqsub, Basic)
4683 DEFINE_TEST_NEON_3SAME_SCALAR(sqsub, Basic)
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| /third_party/vixl/src/aarch64/ |
| H A D | assembler-aarch64.h | 2533 void sqsub(const VRegister& vd, const VRegister& vn, const VRegister& vm);
5496 void sqsub(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
5499 void sqsub(const ZRegister& zd,
6523 void sqsub(const ZRegister& zd,
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| H A D | macro-assembler-sve-aarch64.cc | 676 V(Sqsub, sqsub) \
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| H A D | assembler-sve-aarch64.cc | 2280 void Assembler::sqsub(const ZRegister& zd, in sqsub() function in vixl::aarch64::Assembler
3711 void Assembler::sqsub(const ZRegister& zd, in sqsub() function in vixl::aarch64::Assembler
8547 void Assembler::sqsub(const ZRegister& zd, in sqsub() function in vixl::aarch64::Assembler
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| H A D | macro-assembler-aarch64.h | 2935 V(sqsub, Sqsub) \
6048 sqsub(zd, zn, zm); in Sqsub()
6055 sqsub(zd, zd, imm.AsUint16()); in Sqsub()
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| H A D | assembler-aarch64.cc | 4210 V(sqsub, NEON_SQSUB, true) \
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1991 void sqsub(const VRegister& vd, const VRegister& vn, const VRegister& vm);
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| H A D | macro-assembler-arm64.h | 433 V(sqsub, Sqsub) \
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| H A D | assembler-arm64.cc | 3106 V(sqsub, NEON_SQSUB, true) \
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