| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 1667 __ sqshlu(b13, b14, 6); in GenerateTestSequenceNEON()
1668 __ sqshlu(d0, d16, 44); in GenerateTestSequenceNEON()
1669 __ sqshlu(h5, h29, 15); in GenerateTestSequenceNEON()
1670 __ sqshlu(s29, s8, 13); in GenerateTestSequenceNEON()
1671 __ sqshlu(v27.V16B(), v20.V16B(), 2); in GenerateTestSequenceNEON()
1672 __ sqshlu(v24.V2D(), v12.V2D(), 11); in GenerateTestSequenceNEON()
1673 __ sqshlu(v12.V2S(), v19.V2S(), 22); in GenerateTestSequenceNEON()
1674 __ sqshlu(v8.V4H(), v12.V4H(), 11); in GenerateTestSequenceNEON()
1675 __ sqshlu(v18.V4S(), v3.V4S(), 8); in GenerateTestSequenceNEON()
1676 __ sqshlu(v in GenerateTestSequenceNEON()
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| H A D | test-cpu-features-aarch64.cc | 1855 TEST_NEON(sqshlu_0, sqshlu(v0.V8B(), v1.V8B(), 4))
1856 TEST_NEON(sqshlu_1, sqshlu(v0.V16B(), v1.V16B(), 7))
1857 TEST_NEON(sqshlu_2, sqshlu(v0.V4H(), v1.V4H(), 14))
1858 TEST_NEON(sqshlu_3, sqshlu(v0.V8H(), v1.V8H(), 15))
1859 TEST_NEON(sqshlu_4, sqshlu(v0.V2S(), v1.V2S(), 13))
1860 TEST_NEON(sqshlu_5, sqshlu(v0.V4S(), v1.V4S(), 6))
1861 TEST_NEON(sqshlu_6, sqshlu(v0.V2D(), v1.V2D(), 42))
1862 TEST_NEON(sqshlu_7, sqshlu(b0, b1, 3))
1863 TEST_NEON(sqshlu_8, sqshlu(h0, h1, 15))
1864 TEST_NEON(sqshlu_9, sqshlu(s
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| H A D | test-disasm-sve-aarch64.cc | 6522 COMPARE(sqshlu(z10.VnB(), p1.Merging(), z10.VnB(), 0), in TEST()
6523 "sqshlu z10.b, p1/m, z10.b, #0"); in TEST()
6524 COMPARE(sqshlu(z10.VnB(), p1.Merging(), z10.VnB(), 2), in TEST()
6525 "sqshlu z10.b, p1/m, z10.b, #2"); in TEST()
6526 COMPARE(sqshlu(z10.VnB(), p1.Merging(), z10.VnB(), 5), in TEST()
6527 "sqshlu z10.b, p1/m, z10.b, #5"); in TEST()
6528 COMPARE(sqshlu(z10.VnB(), p1.Merging(), z10.VnB(), 7), in TEST()
6529 "sqshlu z10.b, p1/m, z10.b, #7"); in TEST()
6530 COMPARE(sqshlu(z10.VnH(), p1.Merging(), z10.VnH(), 0), in TEST()
6531 "sqshlu z1 in TEST()
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| H A D | test-simulator-aarch64.cc | 4794 DEFINE_TEST_NEON_2OPIMM(sqshlu, Basic, TypeWidthFromZero)
4826 DEFINE_TEST_NEON_2OPIMM_SCALAR(sqshlu, Basic, TypeWidthFromZero)
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| H A D | test-api-movprfx-aarch64.cc | 2256 __ sqshlu(z10.VnB(), p1.Merging(), z10.VnB(), 0); in TEST()
3634 __ sqshlu(z10.VnB(), p1.Merging(), z10.VnB(), 0); in TEST()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1937 void sqshlu(const VRegister& vd, const VRegister& vn, int shift);
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| H A D | macro-assembler-arm64.h | 1228 V(sqshlu, Sqshlu) \
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| H A D | assembler-arm64.cc | 1650 void Assembler::sqshlu(const VRegister& vd, const VRegister& vn, int shift) { in sqshlu() function in v8::internal::Assembler
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 1933 LogicVRegister sqshlu(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 5750 sqshlu(vf, rd, rn, left_shift);
5849 sqshlu(vf, rd, rn, left_shift);
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| H A D | simulator-logic-arm64.cc | 1425 LogicVRegister Simulator::sqshlu(VectorFormat vform, LogicVRegister dst, in sqshlu() function in v8::internal::Simulator
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| /third_party/vixl/src/aarch64/ |
| H A D | assembler-aarch64.h | 2995 void sqshlu(const VRegister& vd, const VRegister& vn, int shift);
6505 void sqshlu(const ZRegister& zd,
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| H A D | simulator-aarch64.cc | 3528 sqshlu(vform, result, zdn, left_shift_dist); in Simulator()
9333 sqshlu(vf, rd, rn, left_shift); in Simulator()
9436 sqshlu(vf, rd, rn, left_shift); in Simulator()
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| H A D | simulator-aarch64.h | 4228 LogicVRegister sqshlu(VectorFormat vform,
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| H A D | macro-assembler-aarch64.h | 3171 V(sqshlu, Sqshlu) \
7193 sqshlu(zd, pg, zd, shift); in Sqshlu()
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| H A D | assembler-aarch64.cc | 5562 void Assembler::sqshlu(const VRegister& vd, const VRegister& vn, int shift) {
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| H A D | assembler-sve-aarch64.cc | 8529 void Assembler::sqshlu(const ZRegister& zd, in sqshlu() function in vixl::aarch64::Assembler
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| H A D | logic-aarch64.cc | 1704 LogicVRegister Simulator::sqshlu(VectorFormat vform,
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