| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 1645 __ sqshl(b6, b21, b8); in GenerateTestSequenceNEON()
1646 __ sqshl(b11, b26, 2); in GenerateTestSequenceNEON()
1647 __ sqshl(d29, d0, d4); in GenerateTestSequenceNEON()
1648 __ sqshl(d21, d7, 35); in GenerateTestSequenceNEON()
1649 __ sqshl(h20, h25, h17); in GenerateTestSequenceNEON()
1650 __ sqshl(h20, h0, 8); in GenerateTestSequenceNEON()
1651 __ sqshl(s29, s13, s4); in GenerateTestSequenceNEON()
1652 __ sqshl(s10, s11, 20); in GenerateTestSequenceNEON()
1653 __ sqshl(v8.V16B(), v18.V16B(), v28.V16B()); in GenerateTestSequenceNEON()
1654 __ sqshl(v2 in GenerateTestSequenceNEON()
[all...] |
| H A D | test-cpu-features-aarch64.cc | 1866 TEST_NEON(sqshl_0, sqshl(v0.V8B(), v1.V8B(), 6))
1867 TEST_NEON(sqshl_1, sqshl(v0.V16B(), v1.V16B(), 6))
1868 TEST_NEON(sqshl_2, sqshl(v0.V4H(), v1.V4H(), 8))
1869 TEST_NEON(sqshl_3, sqshl(v0.V8H(), v1.V8H(), 9))
1870 TEST_NEON(sqshl_4, sqshl(v0.V2S(), v1.V2S(), 28))
1871 TEST_NEON(sqshl_5, sqshl(v0.V4S(), v1.V4S(), 27))
1872 TEST_NEON(sqshl_6, sqshl(v0.V2D(), v1.V2D(), 50))
1873 TEST_NEON(sqshl_7, sqshl(b0, b1, 4))
1874 TEST_NEON(sqshl_8, sqshl(h0, h1, 13))
1875 TEST_NEON(sqshl_9, sqshl(s
[all...] |
| H A D | test-simulator-aarch64.cc | 4606 DEFINE_TEST_NEON_3SAME(sqshl, Basic)
4687 DEFINE_TEST_NEON_3SAME_SCALAR(sqshl, Basic)
4778 DEFINE_TEST_NEON_2OPIMM(sqshl, Basic, TypeWidthFromZero)
4813 DEFINE_TEST_NEON_2OPIMM_SCALAR(sqshl, Basic, TypeWidthFromZero)
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| H A D | test-disasm-sve-aarch64.cc | 6501 COMPARE(sqshl(z0.VnB(), p5.Merging(), z0.VnB(), 0), in TEST()
6502 "sqshl z0.b, p5/m, z0.b, #0"); in TEST()
6503 COMPARE(sqshl(z0.VnB(), p5.Merging(), z0.VnB(), 2), in TEST()
6504 "sqshl z0.b, p5/m, z0.b, #2"); in TEST()
6505 COMPARE(sqshl(z0.VnB(), p5.Merging(), z0.VnB(), 5), in TEST()
6506 "sqshl z0.b, p5/m, z0.b, #5"); in TEST()
6507 COMPARE(sqshl(z0.VnB(), p5.Merging(), z0.VnB(), 7), in TEST()
6508 "sqshl z0.b, p5/m, z0.b, #7"); in TEST()
6509 COMPARE(sqshl(z0.VnH(), p5.Merging(), z0.VnH(), 0), in TEST()
6510 "sqshl z in TEST()
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| H A D | test-api-movprfx-aarch64.cc | 2247 __ sqshl(z0.VnB(), p5.Merging(), z0.VnB(), 0); in TEST()
2250 __ sqshl(z0.VnB(), p5.Merging(), z0.VnB(), z2.VnB()); in TEST()
3437 __ sqshl(z0.VnB(), p5.Merging(), z0.VnB(), z0.VnB()); in TEST()
3625 __ sqshl(z0.VnB(), p5.Merging(), z0.VnB(), 0); in TEST()
3628 __ sqshl(z0.VnB(), p5.Merging(), z0.VnB(), z2.VnB()); in TEST()
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| /third_party/ffmpeg/libavcodec/aarch64/ |
| H A D | vp9lpf_16bpp_neon.S | 127 sqshl \tmp1\().8h, \tmp1\().8h, \tmp2\().8h
144 sqshl \tmp1\().8h, \tmp3\().8h, \tmp2\().8h
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1155 void sqshl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
1934 void sqshl(const VRegister& vd, const VRegister& vn, int shift);
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| H A D | macro-assembler-arm64.h | 432 V(sqshl, Sqshl) \
1227 V(sqshl, Sqshl) \
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| H A D | assembler-arm64.cc | 1646 void Assembler::sqshl(const VRegister& vd, const VRegister& vn, int shift) { in sqshl() function in v8::internal::Assembler
3107 V(sqshl, NEON_SQSHL, true) \
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| /third_party/vixl/src/aarch64/ |
| H A D | assembler-aarch64.h | 2716 void sqshl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
2992 void sqshl(const VRegister& vd, const VRegister& vn, int shift);
6487 void sqshl(const ZRegister& zd,
6493 void sqshl(const ZRegister& zd,
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| H A D | macro-assembler-sve-aarch64.cc | 675 V(Sqshl, sqshl) \
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| H A D | macro-assembler-aarch64.h | 2934 V(sqshl, Sqshl) \
3170 V(sqshl, Sqshl) \
7181 sqshl(zd, pg, zd, shift); in Sqshl()
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| H A D | simulator-aarch64.cc | 3525 sqshl(vform, result, zdn, left_shift_dist); in Simulator()
9327 sqshl(vf, rd, rn, left_shift); in Simulator()
9466 sqshl(vf, rd, rn, left_shift); in Simulator()
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| H A D | simulator-aarch64.h | 4220 LogicVRegister sqshl(VectorFormat vform,
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| H A D | assembler-aarch64.cc | 4211 V(sqshl, NEON_SQSHL, true) \
5556 void Assembler::sqshl(const VRegister& vd, const VRegister& vn, int shift) {
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| H A D | assembler-sve-aarch64.cc | 8478 void Assembler::sqshl(const ZRegister& zd, in sqshl() function in vixl::aarch64::Assembler
8495 void Assembler::sqshl(const ZRegister& zd, in sqshl() function in vixl::aarch64::Assembler
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| H A D | logic-aarch64.cc | 1682 LogicVRegister Simulator::sqshl(VectorFormat vform,
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 1929 LogicVRegister sqshl(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 5744 sqshl(vf, rd, rn, left_shift);
5879 sqshl(vf, rd, rn, left_shift);
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| H A D | simulator-logic-arm64.cc | 1409 LogicVRegister Simulator::sqshl(VectorFormat vform, LogicVRegister dst, in sqshl() function in v8::internal::Simulator
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