| /third_party/ffmpeg/libavresample/aarch64/ |
| H A D | audio_convert_neon.S | 38 sqrshrn2 v4.8h, v5.4s, #16
43 sqrshrn2 v6.8h, v7.4s, #16
56 sqrshrn2 v4.8h, v5.4s, #16
60 sqrshrn2 v6.8h, v7.4s, #16
64 sqrshrn2 v4.8h, v5.4s, #16
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| /third_party/ffmpeg/libswresample/aarch64/ |
| H A D | audio_convert_neon.S | 39 sqrshrn2 v4.8h, v5.4s, #16
44 sqrshrn2 v6.8h, v7.4s, #16
57 sqrshrn2 v4.8h, v5.4s, #16
61 sqrshrn2 v6.8h, v7.4s, #16
65 sqrshrn2 v4.8h, v5.4s, #16
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| /third_party/ffmpeg/libavcodec/aarch64/ |
| H A D | hevcdsp_idct_neon.S | 240 sqrshrn2 \d\dt, \n\().4s, \m
435 sqrshrn2 \out0\().8h, \in1, \shift
437 sqrshrn2 \out1\().8h, \in3, \shift
439 sqrshrn2 \out2\().8h, \in5, \shift
441 sqrshrn2 \out3\().8h, \in7, \shift
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1405 void sqrshrn2(const VRegister& vd, const VRegister& vn, int shift);
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| H A D | macro-assembler-arm64.h | 1224 V(sqrshrn2, Sqrshrn2) \
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| H A D | assembler-arm64.cc | 1774 void Assembler::sqrshrn2(const VRegister& vd, const VRegister& vn, int shift) { in sqrshrn2() function in v8::internal::Assembler
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| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 1633 __ sqrshrn2(v19.V16B(), v21.V8H(), 7); in GenerateTestSequenceNEON()
1634 __ sqrshrn2(v29.V4S(), v24.V2D(), 13); in GenerateTestSequenceNEON()
1635 __ sqrshrn2(v12.V8H(), v2.V4S(), 10); in GenerateTestSequenceNEON()
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| H A D | test-cpu-features-aarch64.cc | 1840 TEST_NEON(sqrshrn2_0, sqrshrn2(v0.V16B(), v1.V8H(), 3))
1841 TEST_NEON(sqrshrn2_1, sqrshrn2(v0.V8H(), v1.V4S(), 11))
1842 TEST_NEON(sqrshrn2_2, sqrshrn2(v0.V4S(), v1.V2D(), 25))
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 1979 LogicVRegister sqrshrn2(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 5949 sqrshrn2(vf, rd, rn, right_shift);
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| H A D | simulator-logic-arm64.cc | 2276 LogicVRegister Simulator::sqrshrn2(VectorFormat vform, LogicVRegister dst, in sqrshrn2() function in v8::internal::Simulator
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| /third_party/vixl/src/aarch64/ |
| H A D | simulator-aarch64.h | 4312 LogicVRegister sqrshrn2(VectorFormat vform,
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| H A D | assembler-aarch64.h | 3276 void sqrshrn2(const VRegister& vd, const VRegister& vn, int shift);
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| H A D | assembler-aarch64.cc | 5738 void Assembler::sqrshrn2(const VRegister& vd, const VRegister& vn, int shift) {
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| H A D | logic-aarch64.cc | 3420 LogicVRegister Simulator::sqrshrn2(VectorFormat vform,
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| H A D | macro-assembler-aarch64.h | 3167 V(sqrshrn2, Sqrshrn2) \
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| H A D | simulator-aarch64.cc | 9536 sqrshrn2(vf, rd, rn, right_shift); in Simulator()
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