| /third_party/ffmpeg/libswscale/aarch64/ |
| H A D | yuv2rgb_neon.S | 153 sqdmulh v20.8H, v19.8H, v1.H[0] // V * v2r (R)
154 sqdmulh v22.8H, v18.8H, v1.H[1] // U * u2g
155 sqdmulh v19.8H, v19.8H, v1.H[2] // V * v2g
157 sqdmulh v24.8H, v18.8H, v1.H[3] // U * u2b (B)
169 sqdmulh v26.8H, v26.8H, v0.8H // ((Y1*(1<<3) - y_offset) * y_coeff) >> 15
170 sqdmulh v27.8H, v27.8H, v0.8H // ((Y2*(1<<3) - y_offset) * y_coeff) >> 15
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| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 1569 __ sqdmulh(h17, h27, h12); in GenerateTestSequenceNEON()
1570 __ sqdmulh(h16, h5, v11.H(), 0); in GenerateTestSequenceNEON()
1571 __ sqdmulh(s1, s19, s16); in GenerateTestSequenceNEON()
1572 __ sqdmulh(s1, s16, v2.S(), 0); in GenerateTestSequenceNEON()
1573 __ sqdmulh(v28.V2S(), v1.V2S(), v8.V2S()); in GenerateTestSequenceNEON()
1574 __ sqdmulh(v28.V2S(), v8.V2S(), v3.S(), 0); in GenerateTestSequenceNEON()
1575 __ sqdmulh(v11.V4H(), v25.V4H(), v5.V4H()); in GenerateTestSequenceNEON()
1576 __ sqdmulh(v30.V4H(), v14.V4H(), v8.H(), 5); in GenerateTestSequenceNEON()
1577 __ sqdmulh(v25.V4S(), v21.V4S(), v13.V4S()); in GenerateTestSequenceNEON()
1578 __ sqdmulh(v2 in GenerateTestSequenceNEON()
[all...] |
| H A D | test-cpu-features-aarch64.cc | 1779 TEST_NEON(sqdmulh_0, sqdmulh(v0.V4H(), v1.V4H(), v2.H(), 2))
1780 TEST_NEON(sqdmulh_1, sqdmulh(v0.V8H(), v1.V8H(), v2.H(), 2))
1781 TEST_NEON(sqdmulh_2, sqdmulh(v0.V2S(), v1.V2S(), v2.S(), 1))
1782 TEST_NEON(sqdmulh_3, sqdmulh(v0.V4S(), v1.V4S(), v2.S(), 2))
1783 TEST_NEON(sqdmulh_4, sqdmulh(h0, h1, v2.H(), 2))
1784 TEST_NEON(sqdmulh_5, sqdmulh(s0, s1, v2.S(), 0))
1785 TEST_NEON(sqdmulh_6, sqdmulh(v0.V4H(), v1.V4H(), v2.V4H()))
1786 TEST_NEON(sqdmulh_7, sqdmulh(v0.V8H(), v1.V8H(), v2.V8H()))
1787 TEST_NEON(sqdmulh_8, sqdmulh(v0.V2S(), v1.V2S(), v2.V2S()))
1788 TEST_NEON(sqdmulh_9, sqdmulh(v
[all...] |
| H A D | test-simulator-aarch64.cc | 4619 DEFINE_TEST_NEON_3SAME_HS(sqdmulh, Basic)
4692 DEFINE_TEST_NEON_3SAME_SCALAR_HS(sqdmulh, Basic)
4978 DEFINE_TEST_NEON_BYELEMENT(sqdmulh, Basic, Basic, Basic)
4999 DEFINE_TEST_NEON_BYELEMENT_SCALAR(sqdmulh, Basic, Basic, Basic)
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| H A D | test-api-movprfx-aarch64.cc | 2590 __ sqdmulh(z18.VnB(), z25.VnB(), z1.VnB()); in TEST()
2593 __ sqdmulh(z18.VnH(), z25.VnH(), z1.VnH(), 0); in TEST()
2596 __ sqdmulh(z18.VnS(), z25.VnS(), z1.VnS(), 0); in TEST()
2599 __ sqdmulh(z18.VnD(), z25.VnD(), z1.VnD(), 0); in TEST()
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| /third_party/ffmpeg/libavcodec/aarch64/ |
| H A D | vp8dsp_neon.S | 93 sqdmulh v20.4h, v1.4h, v4.h[1]
94 sqdmulh v23.4h, v3.4h, v4.h[1]
118 sqdmulh v21.4h, v1.4h, v4.h[1]
119 sqdmulh v23.4h, v3.4h, v4.h[1]
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1117 void sqdmulh(const VRegister& vd, const VRegister& vn, const VRegister& vm);
1123 void sqdmulh(const VRegister& vd, const VRegister& vn, const VRegister& vm,
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| H A D | macro-assembler-arm64.h | 222 V(sqdmulh, Sqdmulh) \
427 V(sqdmulh, Sqdmulh) \
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| H A D | assembler-arm64.cc | 3071 V(sqdmulh, NEON_SQDMULH, vd.IsLaneSizeH() || vd.IsLaneSizeS()) \
3329 V(sqdmulh, NEON_SQDMULH_byelement, true) \
|
| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 1684 LogicVRegister sqdmulh(VectorFormat vform, LogicVRegister dst,
1992 LogicVRegister sqdmulh(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 4386 sqdmulh(vf, rd, rn, rm);
4692 Op = &Simulator::sqdmulh;
5571 sqdmulh(vf, rd, rn, rm);
5639 Op = &Simulator::sqdmulh;
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| H A D | simulator-logic-arm64.cc | 897 LogicVRegister Simulator::sqdmulh(VectorFormat vform, LogicVRegister dst, in sqdmulh() function in v8::internal::Simulator
902 return sqdmulh(vform, dst, src1, dup_element(indexform, temp, src2, index)); in sqdmulh()
2748 LogicVRegister Simulator::sqdmulh(VectorFormat vform, LogicVRegister dst, in sqdmulh() function in v8::internal::Simulator
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| /third_party/vixl/src/aarch64/ |
| H A D | assembler-aarch64.h | 3381 void sqdmulh(const VRegister& vd, const VRegister& vn, const VRegister& vm);
3416 void sqdmulh(const VRegister& vd,
6385 void sqdmulh(const ZRegister& zd,
6391 void sqdmulh(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
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| H A D | simulator-aarch64.cc | 2293 sqdmulh(vform, zd, zn, temp); in Simulator()
2557 sqdmulh(vform, zd, zn, zm); in Simulator()
7556 sqdmulh(vf, rd, rn, rm); in Simulator()
8153 sqdmulh(vform, rd, rn, rm, index); in Simulator()
9054 sqdmulh(vf, rd, rn, rm); in Simulator()
9181 Op = &Simulator::sqdmulh; in Simulator()
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| H A D | simulator-aarch64.h | 3569 LogicVRegister sqdmulh(VectorFormat vform,
4396 LogicVRegister sqdmulh(VectorFormat vform,
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| H A D | macro-assembler-aarch64.h | 2925 V(sqdmulh, Sqdmulh) \
3117 V(sqdmulh, Sqdmulh) \
7071 sqdmulh(zd, zn, zm, index); in Sqdmulh()
7076 sqdmulh(zd, zn, zm); in Sqdmulh()
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| H A D | logic-aarch64.cc | 855 LogicVRegister Simulator::sqdmulh(VectorFormat vform, in sqdmulh() function in vixl::aarch64::Simulator
862 return sqdmulh(vform, dst, src1, dup_element(indexform, temp, src2, index)); in sqdmulh()
4234 LogicVRegister Simulator::sqdmulh(VectorFormat vform,
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| H A D | assembler-aarch64.cc | 4175 V(sqdmulh, NEON_SQDMULH, vd.IsLaneSizeH() || vd.IsLaneSizeS()) \
4748 V(sqdmulh, NEON_SQDMULH_byelement, true) \
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| H A D | assembler-sve-aarch64.cc | 8221 void Assembler::sqdmulh(const ZRegister& zd, in sqdmulh() function in vixl::aarch64::Assembler
8242 void Assembler::sqdmulh(const ZRegister& zd, in sqdmulh() function in vixl::aarch64::Assembler
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