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/third_party/ffmpeg/libavcodec/aarch64/
H A Dsimple_idct_neon.S65 smull \a, \b, \c
77 smull\i v7.4S, \y3\l, z2
78 smull\i v16.4S, \y3\l, z6
79 smull\i v17.4S, \y2\l, z1
81 smull\i v18.4S, \y2\l, z3
83 smull\i v5.4S, \y2\l, z5
85 smull\i v6.4S, \y2\l, z7
165 smull v23.4S, v23.4H, z4
174 smull\i v7.4S, v28\l, z4
193 smull\
[all...]
H A Dvp9itxfm_neon.S55 smull \tmp3\().4s, \tmp1\().4h, \tmp4\().h[0]
58 smull \tmp3\().4s, \tmp1\().4h, v0.h[0]
64 smull \tmp3\().4s, \tmp2\().4h, v0.h[0]
69 smull \tmp5\().4s, \tmp2\().4h, v0.h[0]
81 smull \tmp1\().4s, \in1\().4h, v0.h[0]
93 smull \out1\().4s, \in1\().4h, \coef1
95 smull \out3\().4s, \in1\().4h, \coef2
120 smull \tmp1\().4s, \inout1\().4h, \coef1
122 smull \tmp3\().4s, \inout1\().4h, \coef2
132 smull \tmp
[all...]
H A Dvp9mc_16bpp_neon.S185 smull v1.4s, v5.4h, v0.h[0]
186 smull v24.4s, v16.4h, v0.h[0]
192 smull v3.4s, v6.4h, v0.h[0]
193 smull v26.4s, v17.4h, v0.h[0]
389 smull \dst1\().4s, \src1\().4h, v0.h[0]
390 smull \dst2\().4s, \src2\().4h, v0.h[0]
391 smull \tmp1\().4s, \src2\().4h, v0.h[1]
392 smull \tmp2\().4s, \src3\().4h, v0.h[1]
412 smull \dst1\().4s, \src1\().4h, v0.h[0]
414 smull \dst
[all...]
H A Dhevcdsp_idct_neon.S251 smull\p1 v30.4s, \in1, v0.h[1]
252 smull\p1 v31.4s, \in1, v0.h[3]
283 smull\p1 v30.4s, \in1\in1t, v0.h[6]
284 smull\p1 v28.4s, \in1\in1t, v0.h[4]
285 smull\p1 v29.4s, \in1\in1t, v0.h[5]
303 smull\p1 v31.4s, \in1\in1t, v0.h[7]
491 smull v21.4s, v20.4h, v1.h[0]
492 smull v22.4s, v20.4h, v1.h[1]
493 smull v23.4s, v20.4h, v1.h[2]
494 smull v2
[all...]
H A Dvp9itxfm_16bpp_neon.S104 smull \tmp3\().2d, \tmp1\().2s, \tmp4\().s[0]
107 smull \tmp3\().2d, \tmp1\().2s, v0.s[0]
113 smull \tmp3\().2d, \tmp2\().2s, v0.s[0]
118 smull \tmp5\().2d, \tmp2\().2s, v0.s[0]
130 smull \tmp1\().2d, \in1\().2s, v0.s[0]
142 smull \out1\().2d, \in1\().2s, \coef1
144 smull \out3\().2d, \in1\().2s, \coef2
169 smull \tmp1\().2d, \inout1\().2s, \coef1
171 smull \tmp3\().2d, \inout1\().2s, \coef2
181 smull \tmp
[all...]
H A Dvp8dsp_neon.S91 smull v26.4s, v1.4h, v4.h[0]
92 smull v27.4s, v3.4h, v4.h[0]
114 smull v26.4s, v1.4h, v4.h[0]
116 smull v27.4s, v3.4h, v4.h[0]
/third_party/ffmpeg/libavfilter/aarch64/
H A Dvf_nlmeans_neon.S53 smull v4.4S, v2.4H, v2.4H // d[x + 0..3]^2
56 smull v6.4S, v3.4H, v3.4H // d[x + 8..11]^2
/third_party/ffmpeg/libavcodec/arm/
H A Dmlpdsp_armv5te.S93 smull AC0, AC1, CO\index, ST\index
478 smull AC0, AC1, CO0, SA0
485 smull AC0, AC1, CO0, SA0
499 smull AC0, AC1, CO2, SA2
H A Dmpegaudiodsp_fixed_armv6.S94 smull r4, r7, r11, r12
/third_party/ffmpeg/libavresample/aarch64/
H A Dresample_neon.S190 smull \d\().4s, \r0\().4h, \r1\().4h
221 smull \d1\().2d, \r0\().2s, \r1\().2s
/third_party/skia/third_party/externals/freetype/include/freetype/internal/
H A Dftcalc.h55 smull t2, t, b, a /* (lo=t2,hi=t) = a*b */ in FT_MulFix_arm()
87 "smull %1, %2, %4, %3\n\t" /* (lo=%1,hi=%2) = a*b */ in FT_MulFix_arm()
/third_party/ffmpeg/libswscale/aarch64/
H A Dhscale.S233 smull v0.4S, v5.4H, v6.4H // 4 iterations of src[...] * filter[...]
/third_party/node/deps/v8/src/codegen/arm64/
H A Dassembler-arm64.h748 void smull(const Register& rd, const Register& rn, const Register& rm);
1017 void smull(const VRegister& vd, const VRegister& vn, const VRegister& vm,
1486 void smull(const VRegister& vd, const VRegister& vn, const VRegister& vm);
H A Dmacro-assembler-arm64.h230 V(smull, Smull) \
421 V(smull, Smull) \
H A Dmacro-assembler-arm64-inl.h942 smull(rd, rn, rm); in Smull()
H A Dassembler-arm64.cc1140 void Assembler::smull(const Register& rd, const Register& rn, in smull() function in v8::internal::Assembler
1489 V(smull, NEON_SMULL, vn.IsVector() && vn.IsD()) \
3362 V(smull, NEON_SMULL_byelement, vn.IsVector() && vn.IsD()) \
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-arm64.h1630 LogicVRegister smull(VectorFormat vform, LogicVRegister dst,
2014 V(smull) \
H A Dsimulator-logic-arm64.cc735 LogicVRegister Simulator::smull(VectorFormat vform, LogicVRegister dst, in smull() function in v8::internal::Simulator
741 return smull(vform, dst, src1, dup_element(indexform, temp, src2, index)); in smull()
2573 LogicVRegister Simulator::smull(VectorFormat vform, LogicVRegister dst, in smull() function in v8::internal::Simulator
2709 LogicVRegister product = smull(vform, temp, src1, src2); in sqdmull()
/third_party/vixl/test/aarch64/
H A Dtest-trace-aarch64.cc1513 __ smull(v4.V2D(), v29.V2S(), v17.V2S()); in GenerateTestSequenceNEON()
1514 __ smull(v30.V2D(), v21.V2S(), v6.S(), 2); in GenerateTestSequenceNEON()
1515 __ smull(v23.V4S(), v5.V4H(), v23.V4H()); in GenerateTestSequenceNEON()
1516 __ smull(v8.V4S(), v9.V4H(), v2.H(), 1); in GenerateTestSequenceNEON()
1517 __ smull(v31.V8H(), v17.V8B(), v1.V8B()); in GenerateTestSequenceNEON()
H A Dtest-cpu-features-aarch64.cc432 TEST_NONE(smull_0, smull(x0, w1, w2))
1723 TEST_NEON(smull_0, smull(v0.V4S(), v1.V4H(), v2.H(), 6))
1724 TEST_NEON(smull_1, smull(v0.V2D(), v1.V2S(), v2.S(), 3))
1727 TEST_NEON(smull_2, smull(v0.V8H(), v1.V8B(), v2.V8B()))
1728 TEST_NEON(smull_3, smull(v0.V4S(), v1.V4H(), v2.V4H()))
1729 TEST_NEON(smull_4, smull(v0.V2D(), v1.V2S(), v2.V2S()))
H A Dtest-simulator-aarch64.cc4739 DEFINE_TEST_NEON_3DIFF_LONG(smull, Basic)
4976 DEFINE_TEST_NEON_BYELEMENT_DIFF(smull, Basic, Basic, Basic)
/third_party/node/deps/v8/src/codegen/arm/
H A Dassembler-arm.h525 void smull(Register dstL, Register dstH, Register src1, Register src2,
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/DartARM32/
H A Dassembler_arm.h516 void smull(Register rd_lo, Register rd_hi, Register rn, Register rm,
/third_party/vixl/src/aarch64/
H A Dsimulator-aarch64.cc2325 smull(vform, zd, zn_b, zm_idx); in Simulator()
2329 smull(vform, zd, zn_t, zm_idx); in Simulator()
2841 smull(vform, zd, zn_b, zm_b); in Simulator()
2844 smull(vform, zd, zn_t, zm_t); in Simulator()
7786 smull(vf_l, rd, rn, rm); in Simulator()
7970 smull(vf, rd, rn, temp, is_2); in Simulator()
H A Dassembler-aarch64.h993 void smull(const Register& xd, const Register& wn, const Register& wm);
2617 void smull(const VRegister& vd,
3357 void smull(const VRegister& vd, const VRegister& vn, const VRegister& vm);

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