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Searched refs:simm5 (Results 1 - 4 of 4) sorted by relevance

/third_party/node/deps/v8/src/execution/riscv64/
H A Dsimulator-riscv64.cc240 type_sew_t<x>::type simm5 = (type_sew_t<x>::type)(instr_.RvvSimm5()); \
269 type_sew_t<x>::type simm5 = (type_sew_t<x>::type)(instr_.RvvSimm5());
598 type_sew_t<x>::type simm5 = (type_sew_t<x>::type)instr_.RvvSimm5(); \
649 type_sew_t<x>::type simm5 = (type_sew_t<x>::type)instr_.RvvSimm5(); \
5221 USE(simm5);
5229 USE(simm5);
5368 RVV_VI_VI_LOOP({ vd = simm5 + vs2; })
5377 vd = sat_add<int8_t, uint8_t>(vs2, simm5, sat);
5382 vd = sat_add<int16_t, uint16_t>(vs2, simm5, sat);
5387 vd = sat_add<int32_t, uint32_t>(vs2, simm5, sa
[all...]
/third_party/node/deps/v8/src/diagnostics/riscv64/
H A Ddisasm-riscv64.cc301 const int simm5 = instr->RvvSimm5(); in PrintRvvSimm5() local
302 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", simm5); in PrintRvvSimm5()
799 DCHECK(STRING_STARTS_WITH(format, "simm5")); in FormatOption()
2020 Format(instr, "vadd.vi 'vd, 'vs2, 'simm5'vm"); in DecodeRvvIVI()
2023 Format(instr, "vsadd.vi 'vd, 'vs2, 'simm5'vm"); in DecodeRvvIVI()
2026 Format(instr, "vsaddu.vi 'vd, 'vs2, 'simm5'vm"); in DecodeRvvIVI()
2029 Format(instr, "vrsub.vi 'vd, 'vs2, 'simm5'vm"); in DecodeRvvIVI()
2032 Format(instr, "vand.vi 'vd, 'vs2, 'simm5'vm"); in DecodeRvvIVI()
2035 Format(instr, "vor.vi 'vd, 'vs2, 'simm5'vm"); in DecodeRvvIVI()
2038 Format(instr, "vxor.vi 'vd, 'vs2, 'simm5'v in DecodeRvvIVI()
[all...]
/third_party/node/deps/v8/src/codegen/riscv64/
H A Dassembler-riscv64.h716 void vmv_vi(VRegister vd, uint8_t simm5);
1677 void GenInstrV(uint8_t funct6, VRegister vd, int8_t simm5, VRegister vs2,
H A Dassembler-riscv64.cc2504 void Assembler::vmv_vi(VRegister vd, uint8_t simm5) { in vmv_vi() argument
2505 GenInstrV(VMV_FUNCT6, vd, simm5, v0, NoMask); in vmv_vi()

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