| /third_party/ffmpeg/libavcodec/aarch64/ |
| H A D | simple_idct_neon.S | 140 shrn2 \y1\().8H, v22.4S, #ROW_SHIFT
142 shrn2 \y2\().8H, v21.4S, #ROW_SHIFT
143 shrn2 \y3\().8H, v20.4S, #ROW_SHIFT
144 shrn2 \y4\().8H, v19.4S, #ROW_SHIFT
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| H A D | mpegaudiodsp_neon.S | 117 shrn2 v16.4s, v17.2d, #OUT_SHIFT
119 shrn2 v19.4s, v18.2d, #OUT_SHIFT
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| H A D | hpeldsp_neon.S | 343 shrn2 \rd, \rn, \rm
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-logic-arm64.cc | 2117 LogicVRegister Simulator::shrn2(VectorFormat vform, LogicVRegister dst, in shrn2() function in v8::internal::Simulator
2236 return shrn2(vform, dst, src, shift).UnsignedSaturate(vform); in uqshrn2()
2768 shrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in addhn2()
2804 shrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in subhn2()
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| H A D | simulator-arm64.h | 1959 LogicVRegister shrn2(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 5914 shrn2(vf, rd, rn, right_shift);
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| /third_party/vixl/src/aarch64/ |
| H A D | logic-aarch64.cc | 3208 LogicVRegister Simulator::shrn2(VectorFormat vform,
3364 return shrn2(vform, dst, src, shift).UnsignedSaturate(vform);
4259 shrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform));
4303 shrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform));
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| H A D | simulator-aarch64.h | 4272 LogicVRegister shrn2(VectorFormat vform,
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| H A D | assembler-aarch64.h | 3246 void shrn2(const VRegister& vd, const VRegister& vn, int shift);
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| H A D | assembler-aarch64.cc | 5696 void Assembler::shrn2(const VRegister& vd, const VRegister& vn, int shift) {
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| H A D | macro-assembler-aarch64.h | 3164 V(shrn2, Shrn2) \
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| H A D | simulator-aarch64.cc | 9501 shrn2(vf, rd, rn, right_shift); in Simulator()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1375 void shrn2(const VRegister& vd, const VRegister& vn, int shift);
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| H A D | macro-assembler-arm64.h | 1221 V(shrn2, Shrn2) \
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| H A D | assembler-arm64.cc | 1744 void Assembler::shrn2(const VRegister& vd, const VRegister& vn, int shift) { in shrn2() function in v8::internal::Assembler
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| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 1437 __ shrn2(v5.V16B(), v30.V8H(), 3); in GenerateTestSequenceNEON()
1438 __ shrn2(v24.V4S(), v1.V2D(), 1); in GenerateTestSequenceNEON()
1439 __ shrn2(v5.V8H(), v14.V4S(), 16); in GenerateTestSequenceNEON()
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| H A D | test-cpu-features-aarch64.cc | 1647 TEST_NEON(shrn2_0, shrn2(v0.V16B(), v1.V8H(), 2))
1648 TEST_NEON(shrn2_1, shrn2(v0.V8H(), v1.V4S(), 14))
1649 TEST_NEON(shrn2_2, shrn2(v0.V4S(), v1.V2D(), 18))
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