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Searched refs:shll2 (Results 1 - 14 of 14) sorted by relevance

/third_party/node/deps/v8/src/codegen/arm64/
H A Dassembler-arm64.h1964 void shll2(const VRegister& vd, const VRegister& vn, int shift);
H A Dmacro-assembler-arm64.h1219 V(shll2, Shll2) \
H A Dassembler-arm64.cc2915 void Assembler::shll2(const VRegister& vd, const VRegister& vn, int shift) { in shll2() function in v8::internal::Assembler
/third_party/vixl/src/aarch64/
H A Dmacro-assembler-aarch64.h3162 V(shll2, Shll2) \
3203 V(shll2, sshll2, Sshll2) \
3204 V(shll2, ushll2, Ushll2)
H A Dsimulator-aarch64.h4169 LogicVRegister shll2(VectorFormat vform,
H A Dassembler-aarch64.h3022 void shll2(const VRegister& vd, const VRegister& vn, int shift);
H A Dassembler-aarch64.cc4036 void Assembler::shll2(const VRegister& vd, const VRegister& vn, int shift) {
H A Dlogic-aarch64.cc1544 LogicVRegister Simulator::shll2(VectorFormat vform, in shll2() function in vixl::aarch64::Simulator
H A Dsimulator-aarch64.cc7205 shll2(vf, rd, rn); in Simulator()
/third_party/vixl/test/aarch64/
H A Dtest-trace-aarch64.cc1431 __ shll2(v21.V2D(), v28.V4S(), 32); in GenerateTestSequenceNEON()
1432 __ shll2(v22.V4S(), v1.V8H(), 16); in GenerateTestSequenceNEON()
1433 __ shll2(v30.V8H(), v25.V16B(), 8); in GenerateTestSequenceNEON()
H A Dtest-cpu-features-aarch64.cc1633 TEST_NEON(shll2_0, shll2(v0.V8H(), v1.V16B(), 8))
1634 TEST_NEON(shll2_1, shll2(v0.V4S(), v1.V8H(), 16))
1635 TEST_NEON(shll2_2, shll2(v0.V2D(), v1.V4S(), 32))
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-arm64.h1903 LogicVRegister shll2(VectorFormat vform, LogicVRegister dst,
H A Dsimulator-arm64.cc4157 shll2(vf, rd, rn);
H A Dsimulator-logic-arm64.cc1371 LogicVRegister Simulator::shll2(VectorFormat vform, LogicVRegister dst, in shll2() function in v8::internal::Simulator

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