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/third_party/node/test/parallel/
H A Dtest-stream-buffer-list.js47 const shifted = list.shift();
49 assert.strictEqual(shifted, buf);
/third_party/mesa3d/src/intel/vulkan/
H A Danv_nir_lower_multiview.c115 nir_ssa_def *shifted; in build_view_index() local
117 shifted = nir_ushr(b, nir_imm_int(b, remap), shift); in build_view_index()
124 shifted = nir_bcsel(b, nir_ilt(b, shift, nir_imm_int(b, 32)), in build_view_index()
127 state->view_index = nir_iand(b, shifted, nir_imm_int(b, 0xf)); in build_view_index()
/third_party/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_format_srgb.c358 LLVMValueRef shifted, shift_val; in lp_build_float_to_srgb_packed() local
361 shifted = LLVMBuildShl(builder, tmpsrgb[chan], shift_val, ""); in lp_build_float_to_srgb_packed()
362 dst = LLVMBuildOr(builder, dst, shifted, ""); in lp_build_float_to_srgb_packed()
H A Dlp_bld_swizzle.c522 LLVMValueRef shifted; in lp_build_swizzle_aos() local
529 shifted = LLVMBuildShl(builder, masked, in lp_build_swizzle_aos()
532 shifted = LLVMBuildLShr(builder, masked, in lp_build_swizzle_aos()
535 shifted = masked; in lp_build_swizzle_aos()
538 res = LLVMBuildOr(builder, res, shifted, ""); in lp_build_swizzle_aos()
H A Dlp_bld_format_aos.c226 LLVMValueRef shifted, casted, scaled, masked; in lp_build_unpack_arith_rgba_aos() local
328 shifted = LLVMBuildLShr(builder, packed, LLVMConstVector(shifts, 4), ""); in lp_build_unpack_arith_rgba_aos()
329 masked = LLVMBuildAnd(builder, shifted, LLVMConstVector(masks, 4), ""); in lp_build_unpack_arith_rgba_aos()
372 LLVMValueRef shifted, casted, scaled, unswizzled; in lp_build_pack_rgba_aos() local
433 shifted = LLVMBuildShl(builder, casted, LLVMConstVector(shifts, 4), ""); in lp_build_pack_rgba_aos()
438 LLVMValueRef component = LLVMBuildExtractElement(builder, shifted, in lp_build_pack_rgba_aos()
H A Dlp_bld_conv.c921 LLVMValueRef shifted; in lp_build_conv() local
923 shifted = lp_build_shr_imm(&bld, tmp[i], src_shift - 1); in lp_build_conv()
924 tmp[i] = LLVMBuildSub(builder, tmp[i], shifted, ""); in lp_build_conv()
/third_party/mesa3d/src/intel/compiler/
H A Dbrw_vec4_visitor.cpp481 dst_reg shifted(this, glsl_type::uvec4_type); in emit_unpack_unorm_4x8()
483 emit(SHR(shifted, src0, src_reg(shift))); in emit_unpack_unorm_4x8()
485 shifted.type = BRW_REGISTER_TYPE_UB; in emit_unpack_unorm_4x8()
487 emit(VEC4_OPCODE_MOV_BYTES, f, src_reg(shifted)); in emit_unpack_unorm_4x8()
503 dst_reg shifted(this, glsl_type::uvec4_type); in emit_unpack_snorm_4x8()
505 emit(SHR(shifted, src0, src_reg(shift))); in emit_unpack_snorm_4x8()
507 shifted.type = BRW_REGISTER_TYPE_B; in emit_unpack_snorm_4x8()
509 emit(VEC4_OPCODE_MOV_BYTES, f, src_reg(shifted)); in emit_unpack_snorm_4x8()
H A Dbrw_fs_nir.cpp228 fs_reg shifted = abld.vgrf(BRW_REGISTER_TYPE_UW, 1); in emit_system_values_block() local
232 hbld.SHR(offset(shifted, hbld, i), in emit_system_values_block()
247 fs_reg inverted = negate(shifted); in emit_system_values_block()
250 abld.NOT(inverted, shifted); in emit_system_values_block()
4170 * shifted up so that we can stick the SIMD channel index in the middle. This
5664 fs_reg shifted = bld.vgrf(src.type);
5668 allbld.emit(SHADER_OPCODE_SHUFFLE, shifted, scan, idx);
5669 allbld.group(1, 0).MOV(component(shifted, 0), identity);
5670 scan = shifted;
H A Dbrw_fs.cpp1484 * the shading rate divided by two and shifted.
1711 fs_reg shifted = ubld.vgrf(BRW_REGISTER_TYPE_W, 2);
1712 ubld.SHL(horiz_offset(shifted, 8),
1715 ubld.SHL(shifted, horiz_offset(shifted, 8), brw_imm_w(8));
1719 ubld16.group(16, 0).ASR(b32, shifted, brw_imm_w(15));
6438 * instruction), in order to avoid getting a right-shifted
/third_party/mesa3d/src/amd/addrlib/src/core/
H A Daddrelemlib.cpp207 ADDR_FLT_32 shifted; in Flt32sToInt32s() local
236 shifted.f = (scaled.f * 256); in Flt32sToInt32s()
237 truncated = ((shifted.i&0x7FFFFF) + (INT_64)0x800000) << 8; in Flt32sToInt32s()
238 altShift = 126 + 24 + 8 - ((shifted.i>>23)&0xFF); in Flt32sToInt32s()
/third_party/mesa3d/src/compiler/nir/
H A Dnir_format_convert.h197 nir_ssa_def *shifted = nir_ishl(b, nir_channel(b, src, i), in nir_format_bitcast_uvec_unmasked() local
200 dst_chan[dst_idx] = shifted; in nir_format_bitcast_uvec_unmasked()
202 dst_chan[dst_idx] = nir_ior(b, dst_chan[dst_idx], shifted); in nir_format_bitcast_uvec_unmasked()
/third_party/node/deps/openssl/openssl/crypto/modes/asm/
H A Dghash-c64xplus.pl73 SHL $E10000,16,$E10000 ; [pre-shifted] reduction polynomial
101 SHL $E10000,16,$E10000 ; [pre-shifted] reduction polynomial
/third_party/openssl/crypto/modes/asm/
H A Dghash-c64xplus.pl73 SHL $E10000,16,$E10000 ; [pre-shifted] reduction polynomial
101 SHL $E10000,16,$E10000 ; [pre-shifted] reduction polynomial
/third_party/python/PCbuild/
H A Drt.bat12 rem All leading instances of these switches are shifted off, and
/third_party/icu/icu4j/main/tests/collate/src/com/ibm/icu/dev/test/collator/
H A DCollationMiscTest.java918 String[] shifted = { in TestBlackBird()
967 size = shifted.length; in TestBlackBird()
970 String t1 = shifted[i]; in TestBlackBird()
971 String t2 = shifted[j]; in TestBlackBird()
976 size = shifted.length; in TestBlackBird()
978 String t1 = shifted[i-1]; in TestBlackBird()
979 String t2 = shifted[i]; in TestBlackBird()
/third_party/icu/ohos_icu4j/src/main/tests/ohos/global/icu/dev/test/collator/
H A DCollationMiscTest.java921 String[] shifted = { in TestBlackBird()
970 size = shifted.length; in TestBlackBird()
973 String t1 = shifted[i]; in TestBlackBird()
974 String t2 = shifted[j]; in TestBlackBird()
979 size = shifted.length; in TestBlackBird()
981 String t1 = shifted[i-1]; in TestBlackBird()
982 String t2 = shifted[i]; in TestBlackBird()
/third_party/icu/icu4j/main/classes/collate/src/com/ibm/icu/text/
H A DRuleBasedCollator.java591 * Sets the alternate handling for QUATERNARY strength to be either shifted or non-ignorable. See the UCA definition
599 * @param shifted
605 public void setAlternateHandlingShifted(boolean shifted) { in setAlternateHandlingShifted() argument
607 if(shifted == isAlternateHandlingShifted()) { return; } in setAlternateHandlingShifted()
609 ownedSettings.setAlternateHandlingShifted(shifted); in setAlternateHandlingShifted()
/third_party/icu/ohos_icu4j/src/main/java/ohos/global/icu/text/
H A DRuleBasedCollator.java574 * Sets the alternate handling for QUATERNARY strength to be either shifted or non-ignorable. See the UCA definition
582 * @param shifted
587 public void setAlternateHandlingShifted(boolean shifted) { in setAlternateHandlingShifted() argument
589 if(shifted == isAlternateHandlingShifted()) { return; } in setAlternateHandlingShifted()
591 ownedSettings.setAlternateHandlingShifted(shifted); in setAlternateHandlingShifted()
/third_party/ffmpeg/libswscale/
H A Dutils.c2304 SwsVector *shifted = sws_getShiftedVec(a, shift); in sws_shiftVec() local
2305 if (!shifted) { in sws_shiftVec()
2310 a->coeff = shifted->coeff; in sws_shiftVec()
2311 a->length = shifted->length; in sws_shiftVec()
2312 av_free(shifted); in sws_shiftVec()
/third_party/icu/icu4c/source/test/cintltst/
H A Dcmsccoll.c148 const static char shifted[][20] = { variable
211 size = UPRV_LENGTHOF(shifted); in BlackBirdTest()
214 u_uastrcpy(t1, shifted[i]); in BlackBirdTest()
215 u_uastrcpy(t2, shifted[j]); in BlackBirdTest()
223 size = UPRV_LENGTHOF(shifted); in BlackBirdTest()
225 u_uastrcpy(t1, shifted[i-1]); in BlackBirdTest()
226 u_uastrcpy(t2, shifted[i]); in BlackBirdTest()
/third_party/mesa3d/src/nouveau/codegen/
H A Dnv50_ir_lowering_nv50.cpp1897 Value *src[2], *shifted; in handleSULDP() local
1901 shifted = bld.mkOp2v(OP_SHR, TYPE_U16, bld.getSSA(2), src[!!(i & 2)], bld.loadImm(NULL, (uint16_t)8)); in handleSULDP()
1903 shifted = src[!!(i & 2)]; in handleSULDP()
1906 packedType, shifted); in handleSULDP()
/third_party/ffmpeg/tests/fate/
H A Dmatroska.mak96 # which happens to be negative and therefore needs to be shifted.
/third_party/python/Lib/
H A D_pydecimal.py3705 """Returns a shifted copy of self, value-of-other times."""
3734 shifted = rotdig[:torot]
3736 shifted = rotdig + '0'*torot
3737 shifted = shifted[-context.prec:]
3740 shifted.lstrip('0') or '0', self._exp)
5446 """Returns a shifted copy of a, b times.
5448 The coefficient of the result is a shifted copy of the digits
5452 positive or to the right otherwise. Digits shifted into the
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-logic-arm64.cc1402 uint64_t shifted = src_lane << shift; in sli() local
1404 dst.SetUint(vform, i, (dst_lane & ~mask) | shifted); in sli()
1442 uint64_t shifted; in sri() local
1445 shifted = 0; in sri()
1448 shifted = src_lane >> shift; in sri()
1451 dst.SetUint(vform, i, (dst_lane & ~mask) | shifted); in sri()
1582 // Set rounding state by testing most-significant bit shifted out. in sshl()
/third_party/vixl/src/aarch64/
H A Dlogic-aarch64.cc1674 uint64_t shifted = src_lane << shift;
1676 dst.SetUint(vform, i, (dst_lane & ~mask) | shifted);
1726 uint64_t shifted;
1729 shifted = 0;
1732 shifted = src_lane >> shift;
1735 dst.SetUint(vform, i, (dst_lane & ~mask) | shifted);
1935 // Set rounding state by testing most-significant bit shifted out.
7091 // which occupies the corresponding lanes of the value to be shifted.
7096 // Saturate shift_amount to the size of the lane that will be shifted.

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