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Searched refs:sh_base (Results 1 - 5 of 5) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_build_pm4.h301 #define radeon_emit_one_32bit_pointer(sctx, desc, sh_base) do { \
302 unsigned sh_offset = (sh_base) + (desc)->shader_userdata_offset; \
H A Dsi_descriptors.c2086 uint32_t *base = &sctx->shader_pointers.sh_base[shader]; in si_set_user_data_base()
2155 #define si_emit_consecutive_shader_pointers(sctx, pointer_mask, sh_base) do { \
2156 unsigned sh_reg_base = (sh_base); \
2218 uint32_t *sh_base = sctx->shader_pointers.sh_base; in si_emit_graphics_shader_pointers() local
2226 sh_base[PIPE_SHADER_VERTEX]); in si_emit_graphics_shader_pointers()
2228 sh_base[PIPE_SHADER_TESS_EVAL]); in si_emit_graphics_shader_pointers()
2230 sh_base[PIPE_SHADER_FRAGMENT]); in si_emit_graphics_shader_pointers()
2232 sh_base[PIPE_SHADER_TESS_CTRL]); in si_emit_graphics_shader_pointers()
2234 sh_base[PIPE_SHADER_GEOMETR in si_emit_graphics_shader_pointers()
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H A Dsi_state_draw.cpp629 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
1549 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
1904 unsigned sh_base = si_get_user_data_base(GFX_VERSION, HAS_TESS, HAS_GS, NGG,
1951 radeon_set_sh_reg_seq(sh_base + SI_SGPR_VS_VB_DESCRIPTOR_FIRST * 4, num_vb_sgprs);
2023 radeon_set_sh_reg(sh_base + sh_dw_offset * 4,
2035 radeon_set_sh_reg_seq(sh_base + SI_SGPR_VS_VB_DESCRIPTOR_FIRST * 4, num_sgprs);
H A Dsi_state.h247 uint32_t sh_base[SI_NUM_SHADERS]; member
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_cmd_buffer.c1005 uint32_t sh_base = pipeline->user_data_0[stage]; in radv_emit_descriptor_pointers() local
1017 unsigned sh_offset = sh_base + loc->sgpr_idx * 4; in radv_emit_descriptor_pointers()

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