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Searched refs:sgpr_idx (Results 1 - 8 of 8) sorted by relevance

/third_party/mesa3d/src/amd/vulkan/
H A Dradv_shader_args.c34 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs) in set_loc() argument
36 ud_info->sgpr_idx = *sgpr_idx; in set_loc()
38 *sgpr_idx += num_sgprs; in set_loc()
42 set_loc_shader(struct radv_shader_args *args, int idx, uint8_t *sgpr_idx, uint8_t num_sgprs) in set_loc_shader() argument
47 set_loc(ud_info, sgpr_idx, num_sgprs); in set_loc_shader()
51 set_loc_shader_ptr(struct radv_shader_args *args, int idx, uint8_t *sgpr_idx) in set_loc_shader_ptr() argument
57 set_loc_shader(args, idx, sgpr_idx, use_32bit_pointers ? 1 : 2); in set_loc_shader_ptr()
61 set_loc_desc(struct radv_shader_args *args, int idx, uint8_t *sgpr_idx) in set_loc_desc() argument
67 set_loc(ud_info, sgpr_idx, in set_loc_desc()
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H A Dradv_device_generated_commands.c52 if (locs->shader_data[AC_UD_PUSH_CONSTANTS].sgpr_idx >= 0) { in radv_get_sequence_size()
57 if (locs->shader_data[AC_UD_INLINE_PUSH_CONSTANTS].sgpr_idx >= 0) in radv_get_sequence_size()
1180 ((radv_lookup_user_sgpr(&graphics_pipeline->base, MESA_SHADER_VERTEX, AC_UD_VS_VERTEX_BUFFERS)->sgpr_idx * 4 + in radv_prepare_dgc()
1245 if (locs->shader_data[AC_UD_PUSH_CONSTANTS].sgpr_idx >= 0) in radv_prepare_dgc()
1248 if (locs->shader_data[AC_UD_PUSH_CONSTANTS].sgpr_idx >= 0 || in radv_prepare_dgc()
1249 locs->shader_data[AC_UD_INLINE_PUSH_CONSTANTS].sgpr_idx >= 0) { in radv_prepare_dgc()
1253 if (locs->shader_data[AC_UD_PUSH_CONSTANTS].sgpr_idx >= 0) { in radv_prepare_dgc()
1255 (graphics_pipeline->base.user_data_0[i] + 4 * locs->shader_data[AC_UD_PUSH_CONSTANTS].sgpr_idx - in radv_prepare_dgc()
1260 if (locs->shader_data[AC_UD_INLINE_PUSH_CONSTANTS].sgpr_idx >= 0) { in radv_prepare_dgc()
1262 4 * locs->shader_data[AC_UD_INLINE_PUSH_CONSTANTS].sgpr_idx in radv_prepare_dgc()
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H A Dradv_cmd_buffer.c991 if (loc->sgpr_idx == -1) in radv_emit_userdata_address()
996 radv_emit_shader_pointer(device, cs, base_reg + loc->sgpr_idx * 4, va, false); in radv_emit_userdata_address()
1017 unsigned sh_offset = sh_base + loc->sgpr_idx * 4; in radv_emit_descriptor_pointers()
1212 if (loc->sgpr_idx == -1) in radv_emit_inline_push_consts()
1217 radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, loc->num_sgprs); in radv_emit_inline_push_consts()
3300 assert(loc->sgpr_idx != -1); in emit_prolog_inputs()
3302 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, in emit_prolog_inputs()
3543 return loc->sgpr_idx != -1; in radv_shader_loads_push_constants()
3897 if (loc->sgpr_idx == -1) in radv_emit_streamout_buffers()
3902 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx * in radv_emit_streamout_buffers()
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H A Dradv_shader.h190 int8_t sgpr_idx; member
H A Dradv_nir_apply_pipeline_layout.c59 if (user_sgprs_locs->shader_data[AC_UD_INDIRECT_DESCRIPTOR_SETS].sgpr_idx != -1) { in load_desc_ptr()
H A Dradv_nir_to_llvm.c110 if (user_sgprs_locs->shader_data[AC_UD_INDIRECT_DESCRIPTOR_SETS].sgpr_idx != -1) { in load_descriptor_sets()
H A Dradv_pipeline.c6793 return loc->sgpr_idx != -1; in radv_shader_need_indirect_descriptor_sets()
6819 if (loc->sgpr_idx != -1) { in radv_pipeline_init_shader_stages_state()
6821 pipeline->vtx_base_sgpr += loc->sgpr_idx * 4; in radv_pipeline_init_shader_stages_state()
/third_party/mesa3d/src/amd/compiler/
H A Daco_optimizer.cpp3084 uint32_t sgpr_idx = 0; local
3092 sgpr_idx = i;
3096 operand_mask &= ~(1u << sgpr_idx);
3112 if (sgpr_idx == 0)
3115 if (sgpr_idx == 0 || instr->isVOP3() || instr->isSDWA() || instr->isVOP3P() ||
3118 if (info.is_extract() && can_apply_extract(ctx, instr, sgpr_idx, info))
3119 apply_extract(ctx, instr, sgpr_idx, info);
3122 instr->operands[sgpr_idx] = Operand(sgpr);
3124 instr->operands[sgpr_idx] = instr->operands[0];
3131 instr->operands[sgpr_idx]
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