Home
last modified time | relevance | path

Searched refs:sew (Results 1 - 5 of 5) sorted by relevance

/third_party/node/deps/v8/src/codegen/riscv64/
H A Dassembler-riscv64.h1324 inline int32_t sew() const { return 2 ^ (sew_ + 3); } in sew() function in v8::internal::Assembler::VectorUnit
1328 return (kRvvVLEN / sew()) >> (lmul_ & 0b11); in vlmax()
1330 return ((kRvvVLEN << lmul_) / sew()); in vlmax()
1336 void set(Register rd, VSew sew, Vlmul lmul) { in set() argument
1337 if (sew != sew_ || lmul != lmul_ || vl != vlmax()) { in set()
1338 sew_ = sew; in set()
1345 void set(Register rd, int8_t sew, int8_t lmul) { in set() argument
1346 DCHECK_GE(sew, E8); in set()
1347 DCHECK_LE(sew, E64); in set()
1350 set(rd, VSew(sew), Vlmu in set()
1360 set(Register rd, Register rs1, VSew sew, Vlmul lmul) set() argument
1369 set(VSew sew, Vlmul lmul) set() argument
[all...]
H A Dmacro-assembler-riscv64.h957 void WasmRvvExtractLane(Register dst, VRegister src, int8_t idx, VSew sew, in WasmRvvExtractLane() argument
959 VU.set(kScratchReg, sew, lmul); in WasmRvvExtractLane()
967 void WasmRvvEq(VRegister dst, VRegister lhs, VRegister rhs, VSew sew,
970 void WasmRvvNe(VRegister dst, VRegister lhs, VRegister rhs, VSew sew,
972 void WasmRvvGeS(VRegister dst, VRegister lhs, VRegister rhs, VSew sew,
974 void WasmRvvGeU(VRegister dst, VRegister lhs, VRegister rhs, VSew sew,
976 void WasmRvvGtS(VRegister dst, VRegister lhs, VRegister rhs, VSew sew,
978 void WasmRvvGtU(VRegister dst, VRegister lhs, VRegister rhs, VSew sew,
H A Dmacro-assembler-riscv64.cc3924 VSew sew, Vlmul lmul) { in WasmRvvEq()
3925 VU.set(kScratchReg, sew, lmul); in WasmRvvEq()
3933 VSew sew, Vlmul lmul) { in WasmRvvNe()
3934 VU.set(kScratchReg, sew, lmul); in WasmRvvNe()
3942 VSew sew, Vlmul lmul) { in WasmRvvGeS()
3943 VU.set(kScratchReg, sew, lmul); in WasmRvvGeS()
3951 VSew sew, Vlmul lmul) { in WasmRvvGeU()
3952 VU.set(kScratchReg, sew, lmul); in WasmRvvGeU()
3960 VSew sew, Vlmul lmul) { in WasmRvvGtS()
3961 VU.set(kScratchReg, sew, lmu in WasmRvvGtS()
3923 WasmRvvEq(VRegister dst, VRegister lhs, VRegister rhs, VSew sew, Vlmul lmul) WasmRvvEq() argument
3932 WasmRvvNe(VRegister dst, VRegister lhs, VRegister rhs, VSew sew, Vlmul lmul) WasmRvvNe() argument
3941 WasmRvvGeS(VRegister dst, VRegister lhs, VRegister rhs, VSew sew, Vlmul lmul) WasmRvvGeS() argument
3950 WasmRvvGeU(VRegister dst, VRegister lhs, VRegister rhs, VSew sew, Vlmul lmul) WasmRvvGeU() argument
3959 WasmRvvGtS(VRegister dst, VRegister lhs, VRegister rhs, VSew sew, Vlmul lmul) WasmRvvGtS() argument
3968 WasmRvvGtU(VRegister dst, VRegister lhs, VRegister rhs, VSew sew, Vlmul lmul) WasmRvvGtU() argument
[all...]
/third_party/node/deps/v8/src/diagnostics/riscv64/
H A Ddisasm-riscv64.cc291 const char* sew = instr->RvvSEW(); in PrintRvvSEW() local
292 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%s", sew); in PrintRvvSEW()
795 DCHECK(STRING_STARTS_WITH(format, "sew")); in FormatOption()
2636 Format(instr, "vsetvli 'rd, 'rs1, 'sew, 'lmul"); in DecodeVType()
2642 Format(instr, "vsetivli 'rd, 'uimm, 'sew, 'lmul"); in DecodeVType()
/third_party/node/deps/v8/src/compiler/backend/riscv64/
H A Dinstruction-selector-riscv64.cc411 InstructionCode opcode, VSew sew, Vlmul lmul) { in EmitS128Load()
419 g.UseImmediate(index), g.UseImmediate(sew), in EmitS128Load()
428 g.UseImmediate(sew), g.UseImmediate(lmul)); in EmitS128Load()
410 EmitS128Load(InstructionSelector* selector, Node* node, InstructionCode opcode, VSew sew, Vlmul lmul) EmitS128Load() argument

Completed in 23 milliseconds