Searched refs:set_idx (Results 1 - 9 of 9) sorted by relevance
| /third_party/vk-gl-cts/external/openglcts/modules/gl/ |
| H A D | gl4cMapBufferAlignmentTests.cpp | 270 for (size_t set_idx = 0; set_idx < n_storage_flags; ++set_idx) in iterate()
272 const GLenum& storage_set = storage_flags[set_idx]; in iterate()
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| /third_party/mesa3d/src/gallium/drivers/zink/ |
| H A D | zink_descriptors_lazy.c | 50 unsigned set_idx; member
396 if (pool->set_idx == pool->sets_alloc) { in check_pool_alloc()
434 if (pool->set_idx == pool->sets_alloc || unlikely(ctx->dd->has_fbfetch != bdd->has_fbfetch)) { in check_push_pool_alloc()
483 assert(pool->set_idx < pool->sets_alloc); in get_descriptor_set_lazy()
484 return pool->sets[pool->set_idx++]; in get_descriptor_set_lazy()
704 pool->set_idx = 0; in zink_batch_descriptor_reset_lazy()
714 bdd->push_pool[i]->set_idx = 0; in zink_batch_descriptor_reset_lazy()
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| /third_party/mesa3d/src/amd/vulkan/ |
| H A D | radv_descriptor_set.h | 142 void radv_pipeline_layout_add_set(struct radv_pipeline_layout *layout, uint32_t set_idx,
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| H A D | radv_descriptor_set.c | 483 radv_pipeline_layout_add_set(struct radv_pipeline_layout *layout, uint32_t set_idx, in radv_pipeline_layout_add_set() argument
488 if (layout->set[set_idx].layout) in radv_pipeline_layout_add_set()
491 layout->num_sets = MAX2(set_idx + 1, layout->num_sets); in radv_pipeline_layout_add_set()
493 layout->set[set_idx].layout = set_layout; in radv_pipeline_layout_add_set()
500 layout->set[set_idx].dynamic_offset_start = layout->dynamic_offset_count; in radv_pipeline_layout_add_set()
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| H A D | radv_cmd_buffer.c | 5233 unsigned set_idx = i + firstSet; in radv_CmdBindDescriptorSets() local
5249 if (descriptors_state->sets[set_idx] != set || in radv_CmdBindDescriptorSets()
5250 !(descriptors_state->valid & (1u << set_idx))) { in radv_CmdBindDescriptorSets()
5251 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, set_idx); in radv_CmdBindDescriptorSets()
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| /third_party/ffmpeg/libavcodec/ |
| H A D | get_bits.h | 766 static inline int set_idx(GetBitContext *s, int code, int *n, int *nb_bits,
798 code = set_idx(s, code, &n, &nb_bits, table);
801 code = set_idx(s, code, &n, &nb_bits, table);
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| /third_party/mesa3d/src/intel/vulkan/ |
| H A D | anv_nir_apply_pipeline_layout.c | 318 uint32_t set_idx; in build_res_index() local
321 set_idx = set; in build_res_index()
326 set_idx = state->set[set].desc_offset; in build_res_index()
341 const uint32_t packed = (bind_layout->descriptor_stride << 16 ) | (set_idx << 8) | dynamic_offset_index; in build_res_index()
370 nir_ssa_def *set_idx; member
384 defs.set_idx = nir_extract_u8(b, packed, nir_imm_int(b, 1)); in unpack_res_index()
459 nir_load_desc_set_address_intel(b, res.set_idx); in build_desc_addr()
467 return nir_vec2(b, res.set_idx, desc_offset); in build_desc_addr()
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| /third_party/mesa3d/src/microsoft/vulkan/ |
| H A D | dzn_descriptor_set.c | 1602 uint32_t set_idx = 0; in dzn_AllocateDescriptorSets()
1622 for (; set_idx < pool->set_count; set_idx++) { in dzn_AllocateDescriptorSets()
1623 if (!pool->sets[set_idx].layout) { in dzn_AllocateDescriptorSets()
1624 set = &pool->sets[set_idx]; in dzn_AllocateDescriptorSets()
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| /third_party/mesa3d/src/gallium/drivers/r600/sb/ |
| H A D | sb_sched.cpp | 873 alu_node *set_idx = create_set_idx(sh, ar_idx); in load_index_register() local
874 if (!rt.try_reserve(set_idx)) { in load_index_register()
876 dump::dump_op(set_idx); in load_index_register()
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