H A D | aco_lower_to_hw_instr.cpp | 200 PhysReg vtmp_reg, ReduceOp op, unsigned dpp_ctrl, unsigned row_mask, in emit_int64_dpp_op() 215 bld.vop1_dpp(aco_opcode::v_mov_b32, vtmp_def[0], src0[0], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op() 220 dpp_ctrl, row_mask, bank_mask, bound_ctrl); in emit_int64_dpp_op() 223 Operand(vcc, bld.lm), dpp_ctrl, row_mask, bank_mask, bound_ctrl); in emit_int64_dpp_op() 225 bld.vop2_dpp(aco_opcode::v_and_b32, dst[0], src0[0], src1[0], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op() 227 bld.vop2_dpp(aco_opcode::v_and_b32, dst[1], src0[1], src1[1], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op() 230 bld.vop2_dpp(aco_opcode::v_or_b32, dst[0], src0[0], src1[0], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op() 232 bld.vop2_dpp(aco_opcode::v_or_b32, dst[1], src0[1], src1[1], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op() 235 bld.vop2_dpp(aco_opcode::v_xor_b32, dst[0], src0[0], src1[0], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op() 237 bld.vop2_dpp(aco_opcode::v_xor_b32, dst[1], src0[1], src1[1], dpp_ctrl, row_mask, bank_mas in emit_int64_dpp_op() 199 emit_int64_dpp_op(lower_context* ctx, PhysReg dst_reg, PhysReg src0_reg, PhysReg src1_reg, PhysReg vtmp_reg, ReduceOp op, unsigned dpp_ctrl, unsigned row_mask, unsigned bank_mask, bool bound_ctrl, Operand* identity = NULL) emit_int64_dpp_op() argument 386 emit_dpp_op(lower_context* ctx, PhysReg dst_reg, PhysReg src0_reg, PhysReg src1_reg, PhysReg vtmp, ReduceOp op, unsigned size, unsigned dpp_ctrl, unsigned row_mask, unsigned bank_mask, bool bound_ctrl, Operand* identity = NULL) emit_dpp_op() argument 454 emit_dpp_mov(lower_context* ctx, PhysReg dst, PhysReg src0, unsigned size, unsigned dpp_ctrl, unsigned row_mask, unsigned bank_mask, bool bound_ctrl) emit_dpp_mov() argument [all...] |