| /third_party/vixl/test/aarch32/ |
| H A D | test-assembler-cond-rd-rn-t32.cc | 55 M(rev16) \
332 #include "aarch32/traces/assembler-cond-rd-rn-rev16-t32.h"
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| H A D | test-assembler-cond-rd-rn-a32.cc | 55 M(rev16) \
607 #include "aarch32/traces/assembler-cond-rd-rn-rev16-a32.h"
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| /third_party/ffmpeg/libavcodec/aarch64/ |
| H A D | vp9lpf_neon.S | 168 rev16 v1.16b, v0.16b // E
169 rev16 v4.16b, v2.16b // I
170 rev16 v5.16b, v3.16b // H
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 777 void rev16(const Register& rd, const Register& rn);
1904 void rev16(const VRegister& vd, const VRegister& vn);
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| H A D | macro-assembler-arm64-inl.h | 874 rev16(rd, rn); in Rev16()
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| H A D | macro-assembler-arm64.h | 296 V(rev16, Rev16) \
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| H A D | assembler-arm64.cc | 1171 void Assembler::rev16(const Register& rd, const Register& rn) { in rev16() function in v8::internal::Assembler
1956 void Assembler::rev16(const VRegister& vd, const VRegister& vn) { in rev16() function in v8::internal::Assembler
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| /third_party/lzma/Asm/arm64/ |
| H A D | LzmaDecOpt.S | 1118 rev16 sym, sym
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| /third_party/vixl/src/aarch32/ |
| H A D | assembler-aarch32.h | 2874 void rev16(Condition cond, EncodingSize size, Register rd, Register rm);
2875 void rev16(Register rd, Register rm) { rev16(al, Best, rd, rm); } in rev16() function in vixl::aarch32::Assembler
2876 void rev16(Condition cond, Register rd, Register rm) { in rev16() function in vixl::aarch32::Assembler
2877 rev16(cond, Best, rd, rm); in rev16()
2879 void rev16(EncodingSize size, Register rd, Register rm) { in rev16() function in vixl::aarch32::Assembler
2880 rev16(al, size, rd, rm); in rev16()
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| H A D | disasm-aarch32.h | 1028 void rev16(Condition cond, EncodingSize size, Register rd, Register rm);
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| H A D | disasm-aarch32.cc | 2270 void Disassembler::rev16(Condition cond, in rev16() function in vixl::aarch32::Disassembler
8184 rev16(CurrentCond(), Narrow, Register(rd), Register(rm)); in DecodeT32()
21636 rev16(CurrentCond(), in DecodeT32()
21642 rev16(CurrentCond(), in DecodeT32()
[all...] |
| H A D | assembler-aarch32.cc | 8897 void Assembler::rev16(Condition cond, in rev16() function in vixl::aarch32::Assembler
8927 Delegate(kRev16, &Assembler::rev16, cond, size, rd, rm); in rev16()
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| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 275 __ rev16(w20, w21); in GenerateTestSequenceBase()
276 __ rev16(x22, x23); in GenerateTestSequenceBase()
1337 __ rev16(v31.V16B(), v27.V16B()); in GenerateTestSequenceNEON()
1338 __ rev16(v12.V8B(), v26.V8B()); in GenerateTestSequenceNEON()
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| H A D | test-cpu-features-aarch64.cc | 412 TEST_NONE(rev16_0, rev16(w0, w1))
413 TEST_NONE(rev16_1, rev16(x0, x1))
1547 TEST_NEON(rev16_0, rev16(v0.V8B(), v1.V8B()))
1548 TEST_NEON(rev16_1, rev16(v0.V16B(), v1.V16B()))
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| H A D | test-disasm-aarch64.cc | 487 COMPARE(rev16(w4, w5), "rev16 w4, w5"); in TEST()
488 COMPARE(rev16(x6, x7), "rev16 x6, x7"); in TEST()
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| H A D | test-simulator-aarch64.cc | 4840 DEFINE_TEST_NEON_2SAME_8B_16B(rev16, Basic)
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 1722 LogicVRegister rev16(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 3942 rev16(vf, rd, rn);
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| H A D | simulator-logic-arm64.cc | 1912 LogicVRegister Simulator::rev16(VectorFormat vform, LogicVRegister dst, in rev16() function in v8::internal::Simulator
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| /third_party/vixl/src/aarch64/ |
| H A D | assembler-aarch64.h | 1052 void rev16(const Register& rd, const Register& rn);
2962 void rev16(const VRegister& vd, const VRegister& vn);
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| H A D | simulator-aarch64.h | 3661 LogicVRegister rev16(VectorFormat vform,
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| H A D | assembler-aarch64.cc | 1017 void Assembler::rev16(const Register& rd, const Register& rn) { in rev16() function in vixl::aarch64::Assembler
5245 void Assembler::rev16(const VRegister& vd, const VRegister& vn) {
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| H A D | macro-assembler-aarch64.h | 2321 rev16(rd, rn); in Rev16()
3046 V(rev16, Rev16) \
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| H A D | simulator-aarch64.cc | 6972 rev16(vf, rd, rn); in Simulator()
13569 rev16(element_form, result, zn); in Simulator()
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| H A D | logic-aarch64.cc | 2412 LogicVRegister Simulator::rev16(VectorFormat vform,
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