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Searched refs:reg_offset (Results 1 - 25 of 34) sorted by relevance

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/third_party/mesa3d/src/intel/compiler/
H A Dbrw_ir_fs.h181 reg_offset(const fs_reg &r) in reg_offset() function
224 !(reg_offset(r) + dr <= reg_offset(s) || in regions_overlap()
225 reg_offset(s) + ds <= reg_offset(r)); in regions_overlap()
238 reg_offset(r) >= reg_offset(s) && in region_contained_in()
239 reg_offset(r) + dr <= reg_offset(s) + ds; in region_contained_in()
440 * fully or partially) counted from 'floor(reg_offset(ins
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H A Dbrw_ir_vec4.h232 reg_offset(const backend_reg &r) in reg_offset() function
264 !(reg_offset(r) + dr <= reg_offset(s) || in regions_overlap()
265 reg_offset(s) + ds <= reg_offset(r)); in regions_overlap()
413 * fully or partially) counted from 'floor(reg_offset(inst->dst) /
421 return DIV_ROUND_UP(reg_offset(inst->dst) % REG_SIZE + inst->size_written, in regs_written()
427 * fully or partially) counted from 'floor(reg_offset(inst->src[i]) /
436 return DIV_ROUND_UP(reg_offset(inst->src[i]) % reg_size + inst->size_read(i), in regs_read()
H A Dbrw_fs_lower_regioning.cpp114 if (reg_offset(inst->src[i]) % REG_SIZE != in required_dst_byte_offset()
115 reg_offset(inst->dst) % REG_SIZE) in required_dst_byte_offset()
119 return reg_offset(inst->dst) % REG_SIZE; in required_dst_byte_offset()
226 reg_offset(inst->src[i]) % REG_SIZE > 0 && in has_invalid_src_region()
234 const unsigned dst_byte_offset = reg_offset(inst->dst) % REG_SIZE; in has_invalid_src_region()
235 const unsigned src_byte_offset = reg_offset(inst->src[i]) % REG_SIZE; in has_invalid_src_region()
255 const unsigned dst_byte_offset = reg_offset(inst->dst) % REG_SIZE; in has_invalid_dst_region()
H A Dbrw_vec4_visitor.cpp1070 src_reg *reladdr, int reg_offset) in get_scratch_offset()
1085 * to multiply the reladdr by 2. Notice that the reg_offset part in get_scratch_offset()
1092 brw_imm_d(reg_offset))); in get_scratch_offset()
1099 brw_imm_d(reg_offset * message_header_scale))); in get_scratch_offset()
1103 return brw_imm_d(reg_offset * message_header_scale); in get_scratch_offset()
1119 int reg_offset = base_offset + orig_src.offset / REG_SIZE; in emit_scratch_read() local
1121 reg_offset); in emit_scratch_read()
1129 index = get_scratch_offset(block, inst, orig_src.reladdr, reg_offset + 1); in emit_scratch_read()
1148 int reg_offset = base_offset + inst->dst.offset / REG_SIZE; in emit_scratch_write() local
1150 reg_offset); in emit_scratch_write()
1069 get_scratch_offset(bblock_t *block, vec4_instruction *inst, src_reg *reladdr, int reg_offset) get_scratch_offset() argument
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H A Dbrw_vec4.h266 src_reg *reladdr, int reg_offset);
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_build_pm4.h37 #define SI_CHECK_SHADOWED_REGS(reg_offset, count) ac_check_shadowed_regs(GFX10, CHIP_NAVI14, reg_offset, count)
39 #define SI_CHECK_SHADOWED_REGS(reg_offset, count)
308 static inline void radeon_set_sh_reg_func(struct radeon_cmdbuf *cs, unsigned reg_offset, in radeon_set_sh_reg_func() argument
312 radeon_set_sh_reg(reg_offset, value); in radeon_set_sh_reg_func()
316 static inline void radeon_set_sh_reg_idx3_func(struct radeon_cmdbuf *cs, unsigned reg_offset, in radeon_set_sh_reg_idx3_func() argument
320 radeon_set_sh_reg_idx3(reg_offset, value); in radeon_set_sh_reg_idx3_func()
/third_party/ffmpeg/libavcodec/
H A Datrac3plusdsp.c124 * @param[in] reg_offset region offset for trimming envelope data
131 int invert_phase, int reg_offset, float *out) in waves_synth()
145 pos = DEQUANT_PHASE(wave_param->phase_index) - (reg_offset ^ 128) * inc & 2047; in waves_synth()
160 pos = (envelope->start_pos << 2) - reg_offset; in waves_synth()
175 pos = (envelope->stop_pos + 1 << 2) - reg_offset; in waves_synth()
127 waves_synth(Atrac3pWaveSynthParams *synth_param, Atrac3pWavesData *waves_info, Atrac3pWaveEnvelope *envelope, AVFloatDSPContext *fdsp, int invert_phase, int reg_offset, float *out) waves_synth() argument
/third_party/mesa3d/src/amd/common/
H A Dac_shadowed_regs.c4031 unsigned reg_offset = R_02835C_PA_SC_TILE_STEERING_OVERRIDE; in ac_emulate_clear_state() local
4035 gfx11_emulate_clear_state(cs, 1, &reg_offset, &reg_value, set_context_reg_seq_array); in ac_emulate_clear_state()
4037 gfx103_emulate_clear_state(cs, 1, &reg_offset, &reg_value, set_context_reg_seq_array); in ac_emulate_clear_state()
4039 gfx10_emulate_clear_state(cs, 1, &reg_offset, &reg_value, set_context_reg_seq_array); in ac_emulate_clear_state()
4051 unsigned reg_offset, unsigned count) in ac_check_shadowed_regs()
4063 unsigned end_reg_offset = reg_offset + count * 4; in ac_check_shadowed_regs()
4067 if (MAX2(ranges[i].offset, reg_offset) < MIN2(end_range_offset, end_reg_offset)) { in ac_check_shadowed_regs()
4076 if (reg_offset == R_00B858_COMPUTE_DESTINATION_EN_SE0 || in ac_check_shadowed_regs()
4077 reg_offset == R_00B864_COMPUTE_DESTINATION_EN_SE2) in ac_check_shadowed_regs()
4083 printf("%s .. %s\n", ac_get_register_name(gfx_level, reg_offset), in ac_check_shadowed_regs()
4050 ac_check_shadowed_regs(enum amd_gfx_level gfx_level, enum radeon_family family, unsigned reg_offset, unsigned count) ac_check_shadowed_regs() argument
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H A Dac_shadowed_regs.h63 unsigned reg_offset, unsigned count);
H A Dac_shader_util.h134 void ac_set_reg_cu_en(void *cs, unsigned reg_offset, uint32_t value, uint32_t clear_mask,
H A Dac_shader_util.c792 void ac_set_reg_cu_en(void *cs, unsigned reg_offset, uint32_t value, uint32_t clear_mask, in ac_set_reg_cu_en() argument
807 set_sh_reg(cs, reg_offset, new_value); in ac_set_reg_cu_en()
H A Dac_debug.c241 static void ac_parse_set_reg_packet(FILE *f, unsigned count, unsigned reg_offset, in ac_parse_set_reg_packet() argument
245 unsigned reg = ((reg_dw & 0xFFFF) << 2) + reg_offset; in ac_parse_set_reg_packet()
/third_party/mesa3d/src/intel/tools/
H A Daub_read.h53 void (*reg_write)(void *user_data, uint32_t reg_offset, uint32_t reg_value);
/third_party/elfutils/libdw/
H A Ddwarf_frame_register.c76 case reg_offset: in dwarf_frame_register()
H A Dcfi.h127 reg_offset, /* DW_CFA_offset_extended et al */ enumerator
H A Dcfi.c379 fs->regs[regno].rule = reg_offset; in execute_cfi()
/third_party/mesa3d/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_winsys.c125 radv_amdgpu_winsys_read_registers(struct radeon_winsys *rws, unsigned reg_offset, in radv_amdgpu_winsys_read_registers() argument
130 return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers, 0xffffffff, 0, out) == 0; in radv_amdgpu_winsys_read_registers()
/third_party/mesa3d/src/imagination/rogue/
H A Drogue_regalloc.c269 size_t reg_offset = reg_data->offset; in rogue_ra_alloc() local
275 size_t num = phy_reg - reg_offset; in rogue_ra_alloc()
/third_party/mesa3d/src/gallium/drivers/r600/
H A Deg_debug.c134 unsigned reg_offset) in ac_parse_set_reg_packet()
136 unsigned reg = (ib[1] << 2) + reg_offset; in ac_parse_set_reg_packet()
133 ac_parse_set_reg_packet(FILE *f, uint32_t *ib, unsigned count, unsigned reg_offset) ac_parse_set_reg_packet() argument
/third_party/mesa3d/src/gallium/winsys/amdgpu/drm/
H A Damdgpu_winsys.c290 unsigned reg_offset, in amdgpu_read_registers()
295 return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers, in amdgpu_read_registers()
289 amdgpu_read_registers(struct radeon_winsys *rws, unsigned reg_offset, unsigned num_registers, uint32_t *out) amdgpu_read_registers() argument
/third_party/mesa3d/src/gallium/drivers/lima/ir/gp/
H A Dregalloc.c397 unsigned reg_offset = ctx->alloc_start++; in find_free_value_reg() local
405 unsigned cur_reg = (reg_base + reg_offset) % (GPIR_PHYSICAL_REG_NUM + GPIR_VALUE_REG_NUM); in find_free_value_reg()
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_radeon_winsys.h227 bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset, unsigned num_registers,
/third_party/mesa3d/src/gallium/drivers/r600/sb/
H A Dsb_ir.h600 int reg_offset = select.sel() - array->base_gpr.sel(); in get_final_gpr() local
602 reg_offset += rel->get_const_value().i; in get_final_gpr()
603 return array->gpr + (reg_offset << 2); in get_final_gpr()
/third_party/mesa3d/src/panfrost/midgard/
H A Dmidgard_ra.c42 /* Shift up by reg_offset and horizontally by dst_offset. */
45 offset_swizzle(unsigned *swizzle, unsigned reg_offset, unsigned srcshift, unsigned dstshift, unsigned dst_offset) in offset_swizzle() argument
49 signed reg_comp = reg_offset >> srcshift; in offset_swizzle()
54 assert(reg_comp << srcshift == reg_offset); in offset_swizzle()
/third_party/mesa3d/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_winsys.c731 unsigned reg_offset, in radeon_read_registers()
738 uint32_t reg = reg_offset + i*4; in radeon_read_registers()
730 radeon_read_registers(struct radeon_winsys *rws, unsigned reg_offset, unsigned num_registers, uint32_t *out) radeon_read_registers() argument

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