Home
last modified time | relevance | path

Searched refs:reg_index (Results 1 - 25 of 27) sorted by relevance

12

/third_party/node/deps/v8/src/runtime/
H A Druntime-trace.cc45 for (int reg_index = first_reg.index(); reg_index < first_reg.index() + range; in PrintRegisterRange()
46 reg_index++) { in PrintRegisterRange()
47 Object reg_object = frame->ReadInterpreterRegister(reg_index); in PrintRegisterRange()
49 << interpreter::Register(reg_index).ToString() << arrow_direction; in PrintRegisterRange()
/third_party/node/deps/v8/src/builtins/
H A Dbuiltins-generator-gen.cc241 auto reg_index = IntPtrAdd(parameter_base_index, index); in TF_BUILTIN() local
243 TimesSystemPointerSize(reg_index)); in TF_BUILTIN()
260 auto reg_index = IntPtrSub(register_base_index, index); in TF_BUILTIN()
262 TimesSystemPointerSize(reg_index)); in TF_BUILTIN()
300 auto reg_index = IntPtrSub(register_base_index, index); in TF_BUILTIN()
302 TimesSystemPointerSize(reg_index), value); in TF_BUILTIN()
/third_party/node/deps/v8/src/baseline/arm64/
H A Dbaseline-assembler-arm64-inl.h369 for (int reg_index = 0; reg_index < list.register_count(); reg_index += 2) { in Push()
370 PushAll(basm, list[reg_index], list[reg_index + 1]); in Push()
375 int reg_index = list.register_count() - 1; in PushReverse() local
376 if (reg_index % 2 == 0) { in PushReverse()
378 PushAllReverse(basm, list[reg_index], padreg); in PushReverse()
379 reg_index--; in PushReverse()
381 for (; reg_index > in PushReverse()
[all...]
/third_party/node/deps/v8/src/baseline/ia32/
H A Dbaseline-assembler-ia32-inl.h282 for (int reg_index = 0; reg_index < list.register_count(); ++reg_index) { in Push()
283 PushSingle(basm->masm(), list[reg_index]); in Push()
289 for (int reg_index = list.register_count() - 1; reg_index >= 0; in PushReverse()
290 --reg_index) { in PushReverse()
291 PushSingle(basm->masm(), list[reg_index]); in PushReverse()
/third_party/node/deps/v8/src/baseline/loong64/
H A Dbaseline-assembler-loong64-inl.h287 for (int reg_index = 0; reg_index < list.register_count(); ++reg_index) { in Push()
288 PushAllHelper<interpreter::Register>::Push(basm, list[reg_index]); in Push()
294 for (int reg_index = list.register_count() - 1; reg_index >= 0; in PushReverse()
295 --reg_index) { in PushReverse()
296 PushAllHelper<interpreter::Register>::Push(basm, list[reg_index]); in PushReverse()
/third_party/node/deps/v8/src/baseline/ppc/
H A Dbaseline-assembler-ppc-inl.h424 for (int reg_index = 0; reg_index < list.register_count(); ++reg_index) { in Push()
425 PushAllHelper<interpreter::Register>::Push(basm, list[reg_index]); in Push()
431 for (int reg_index = list.register_count() - 1; reg_index >= 0; in PushReverse()
432 --reg_index) { in PushReverse()
433 PushAllHelper<interpreter::Register>::Push(basm, list[reg_index]); in PushReverse()
/third_party/node/deps/v8/src/baseline/x64/
H A Dbaseline-assembler-x64-inl.h286 for (int reg_index = 0; reg_index < list.register_count(); ++reg_index) { in Push()
287 PushSingle(basm->masm(), list[reg_index]); in Push()
293 for (int reg_index = list.register_count() - 1; reg_index >= 0; in PushReverse()
294 --reg_index) { in PushReverse()
295 PushSingle(basm->masm(), list[reg_index]); in PushReverse()
/third_party/mesa3d/src/amd/registers/
H A Dparse_kernel_headers.py820 reg_index = type_map.index(name) if name in type_map else -1
821 if reg_index >= 1 and reg_index % 2 == 1:
822 type_name = type_map[reg_index - 1]
/third_party/node/deps/v8/src/baseline/mips/
H A Dbaseline-assembler-mips-inl.h297 for (int reg_index = 0; reg_index < list.register_count(); ++reg_index) { in Push()
298 PushAllHelper<interpreter::Register>::Push(basm, list[reg_index]); in Push()
304 for (int reg_index = list.register_count() - 1; reg_index >= 0; in PushReverse()
305 --reg_index) { in PushReverse()
306 PushAllHelper<interpreter::Register>::Push(basm, list[reg_index]); in PushReverse()
/third_party/node/deps/v8/src/baseline/s390/
H A Dbaseline-assembler-s390-inl.h422 for (int reg_index = 0; reg_index < list.register_count(); ++reg_index) { in Push()
423 PushAllHelper<interpreter::Register>::Push(basm, list[reg_index]); in Push()
429 for (int reg_index = list.register_count() - 1; reg_index >= 0; in PushReverse()
430 --reg_index) { in PushReverse()
431 PushAllHelper<interpreter::Register>::Push(basm, list[reg_index]); in PushReverse()
/third_party/node/deps/v8/src/baseline/riscv64/
H A Dbaseline-assembler-riscv64-inl.h290 for (int reg_index = 0; reg_index < list.register_count(); ++reg_index) { in Push()
291 PushAllHelper<interpreter::Register>::Push(basm, list[reg_index]); in Push()
297 for (int reg_index = list.register_count() - 1; reg_index >= 0; in PushReverse()
298 --reg_index) { in PushReverse()
299 PushAllHelper<interpreter::Register>::Push(basm, list[reg_index]); in PushReverse()
/third_party/node/deps/v8/src/baseline/mips64/
H A Dbaseline-assembler-mips64-inl.h295 for (int reg_index = 0; reg_index < list.register_count(); ++reg_index) { in Push()
296 PushAllHelper<interpreter::Register>::Push(basm, list[reg_index]); in Push()
302 for (int reg_index = list.register_count() - 1; reg_index >= 0; in PushReverse()
303 --reg_index) { in PushReverse()
304 PushAllHelper<interpreter::Register>::Push(basm, list[reg_index]); in PushReverse()
/third_party/node/deps/v8/src/baseline/arm/
H A Dbaseline-assembler-arm-inl.h305 for (int reg_index = 0; reg_index < list.register_count(); ++reg_index) { in Push()
306 PushAllHelper<interpreter::Register>::Push(basm, list[reg_index]); in Push()
312 for (int reg_index = list.register_count() - 1; reg_index >= 0; in PushReverse()
313 --reg_index) { in PushReverse()
314 PushAllHelper<interpreter::Register>::Push(basm, list[reg_index]); in PushReverse()
/third_party/node/deps/v8/src/interpreter/
H A Dinterpreter-assembler.cc206 TNode<IntPtrT> reg_index) { in RegisterLocation()
208 IntPtrAdd(GetInterpretedFramePointer(), RegisterFrameOffset(reg_index))); in RegisterLocation()
219 TNode<Object> InterpreterAssembler::LoadRegister(TNode<IntPtrT> reg_index) { in LoadRegister() argument
221 RegisterFrameOffset(reg_index)); in LoadRegister()
291 TNode<IntPtrT> reg_index) { in StoreRegister()
293 RegisterFrameOffset(reg_index), value); in StoreRegister()
354 TNode<IntPtrT> InterpreterAssembler::NextRegister(TNode<IntPtrT> reg_index) { in NextRegister() argument
356 return Signed(IntPtrAdd(reg_index, IntPtrConstant(-1))); in NextRegister()
1465 TNode<IntPtrT> reg_index = IntPtrAdd(reg_base, index); in ExportParametersAndRegisterFile() local
1466 TNode<Object> value = LoadRegister(reg_index); in ExportParametersAndRegisterFile()
205 RegisterLocation( TNode<IntPtrT> reg_index) RegisterLocation() argument
290 StoreRegister(TNode<Object> value, TNode<IntPtrT> reg_index) StoreRegister() argument
1490 TNode<IntPtrT> reg_index = ExportParametersAndRegisterFile() local
1535 TNode<IntPtrT> reg_index = ImportRegisterFile() local
[all...]
H A Dinterpreter-assembler.h307 TNode<IntPtrT> RegisterLocation(TNode<IntPtrT> reg_index);
308 TNode<IntPtrT> NextRegister(TNode<IntPtrT> reg_index);
309 TNode<Object> LoadRegister(TNode<IntPtrT> reg_index);
310 void StoreRegister(TNode<Object> value, TNode<IntPtrT> reg_index);
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_shader_llvm_vs.c388 unsigned reg_index; in si_llvm_clipvertex_to_clipdist() local
398 for (reg_index = 0; reg_index < 2; reg_index++) { in si_llvm_clipvertex_to_clipdist()
399 struct ac_export_args *args = &clipdist[reg_index]; in si_llvm_clipvertex_to_clipdist()
401 if (!(clipdist_mask & BITFIELD_RANGE(reg_index * 4, 4))) in si_llvm_clipvertex_to_clipdist()
408 if (!(clipdist_mask & BITFIELD_BIT(reg_index * 4 + chan))) in si_llvm_clipvertex_to_clipdist()
413 LLVMConstInt(ctx->ac.i32, ((reg_index * 4 + chan) * 4 + const_chan) * 4, 0); in si_llvm_clipvertex_to_clipdist()
424 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index; in si_llvm_clipvertex_to_clipdist()
/third_party/node/deps/v8/src/execution/arm/
H A Dsimulator-arm.h430 ReturnType GetFromVFPRegister(int reg_index);
433 void SetVFPRegister(int reg_index, const InputType& value);
H A Dsimulator-arm.cc854 void Simulator::SetVFPRegister(int reg_index, const InputType& value) { in SetVFPRegister() argument
857 DCHECK_GE(reg_index, 0); in SetVFPRegister()
858 if (register_size == 1) DCHECK(reg_index < num_s_registers); in SetVFPRegister()
860 DCHECK(reg_index < DwVfpRegister::SupportedRegisterCount()); in SetVFPRegister()
862 memcpy(&vfp_registers_[reg_index * register_size], &value, bytes); in SetVFPRegister()
866 ReturnType Simulator::GetFromVFPRegister(int reg_index) {
869 DCHECK_GE(reg_index, 0);
870 if (register_size == 1) DCHECK(reg_index < num_s_registers);
872 DCHECK(reg_index < DwVfpRegister::SupportedRegisterCount());
875 memcpy(&value, &vfp_registers_[register_size * reg_index], byte
[all...]
/third_party/node/deps/v8/src/baseline/
H A Dbaseline-compiler.cc146 for (int reg_index = 0; reg_index < list.register_count(); in Check()
147 ++reg_index, ++i) { in Check()
153 list[reg_index])); in Check()
/third_party/mesa3d/src/gallium/drivers/r300/
H A Dr300_reg.h2946 #define PVS_OP_DST_OPERAND(opcode, math_inst, macro_inst, reg_index, reg_writemask, reg_class, saturate) \
2950 | ((reg_index & PVS_DST_OFFSET_MASK) << PVS_DST_OFFSET_SHIFT) \
/third_party/node/deps/v8/src/compiler/backend/
H A Dmid-tier-register-allocator.cc1306 int reg_index = base::bits::CountTrailingZeros(~bits_); in GetFirstCleared() local
1307 if (reg_index < max_reg) { in GetFirstCleared()
1308 return RegisterIndex(reg_index); in GetFirstCleared()
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-arm64.cc4799 int reg_index = imm5 >> lsb;
4805 ins_element(vf, rd, reg_index, rn, rn_index);
4807 ins_immediate(vf, rd, reg_index, xreg(instr->Rn()));
4809 uint64_t value = LogicVRegister(rn).Uint(vf, reg_index);
4813 int64_t value = LogicVRegister(rn).Int(vf, reg_index);
4821 dup_element(vf, rd, rn, reg_index);
/third_party/mesa3d/src/amd/compiler/
H A Daco_register_allocation.cpp889 auto is_free = [&](PhysReg reg_index) in get_reg_simple()
890 { return reg_file[reg_index] == 0 && !ctx.war_hint[reg_index]; }; in get_reg_simple()
/third_party/vixl/test/aarch64/
H A Dtest-assembler-aarch64.cc8277 Register reg_index = x21;
8292 __ Mov(reg_index, size_stored);
8293 __ StoreCPURegList(list_src, MemOperand(reg_base, reg_index));
8294 __ LoadCPURegList(list_dst, MemOperand(reg_base, reg_index));
8301 __ Mov(reg_index, size_stored);
8302 __ StoreCPURegList(list_fp_src_1, MemOperand(reg_base, reg_index));
8303 __ LoadCPURegList(list_fp_dst_1, MemOperand(reg_base, reg_index));
8316 __ Mov(reg_index, size_stored);
8317 __ StoreCPURegList(list_fp_src_2, MemOperand(reg_base, reg_index));
8318 __ LoadCPURegList(list_fp_dst_2, MemOperand(reg_base, reg_index));
[all...]
/third_party/vixl/src/aarch64/
H A Dsimulator-aarch64.cc8176 int reg_index = ExtractSignedBitfield32(31, tz + 1, imm5); in Simulator() local
8181 ins_element(vf, rd, reg_index, rn, rn_index); in Simulator()
8183 ins_immediate(vf, rd, reg_index, ReadXRegister(instr->GetRn())); in Simulator()
8185 uint64_t value = LogicVRegister(rn).Uint(vf, reg_index); in Simulator()
8189 int64_t value = LogicVRegister(rn).Int(vf, reg_index); in Simulator()
8196 dup_element(vf, rd, rn, reg_index); in Simulator()

Completed in 77 milliseconds

12