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Searched refs:reg2 (Results 1 - 25 of 88) sorted by relevance

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/third_party/ffmpeg/libavcodec/loongarch/
H A Dh264_intrapred_lasx.c30 __m256i reg0, reg1, reg2, reg3, reg4; \
73 reg2 = __lasx_xvreplgr2vr_w(res2); \
78 tmp0 = __lasx_xvadd_w(reg2, reg3); \
79 tmp1 = __lasx_xvadd_w(reg2, reg4); \
82 reg2 = __lasx_xvadd_w(reg2, reg1); \
83 tmp2 = __lasx_xvadd_w(reg2, reg3); \
84 tmp3 = __lasx_xvadd_w(reg2, reg4); \
88 reg2 = __lasx_xvadd_w(reg2, reg
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H A Dvp9_idct_lsx.c376 __m128i reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vp9_idct16_1d_columns_addblk_lsx() local
383 reg0, reg1, reg2, reg3); in vp9_idct16_1d_columns_addblk_lsx()
408 VP9_DOTP_CONST_PAIR(reg2, reg14, cospi_28_64, cospi_4_64, reg2, reg14); in vp9_idct16_1d_columns_addblk_lsx()
410 LSX_BUTTERFLY_4_H(reg2, reg14, reg6, reg10, loc0, loc1, reg14, reg2); in vp9_idct16_1d_columns_addblk_lsx()
411 VP9_DOTP_CONST_PAIR(reg14, reg2, cospi_16_64, cospi_16_64, loc2, loc3); in vp9_idct16_1d_columns_addblk_lsx()
414 LSX_BUTTERFLY_4_H(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14); in vp9_idct16_1d_columns_addblk_lsx()
416 reg0 = __lsx_vsub_h(reg2, loc1); in vp9_idct16_1d_columns_addblk_lsx()
417 reg2 in vp9_idct16_1d_columns_addblk_lsx()
502 __m128i reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; vp9_idct16_1d_columns_lsx() local
883 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; vp9_idct8x32_column_even_process_store() local
998 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; vp9_idct8x32_column_odd_process_store() local
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H A Dvp9_mc_lsx.c457 __m128i reg0, reg1, reg2, reg3, reg4; in common_vt_8t_4w_lsx() local
475 reg2 = __lsx_vilvl_d(tmp5, tmp2); in common_vt_8t_4w_lsx()
477 reg2 = __lsx_vxori_b(reg2, 128); in common_vt_8t_4w_lsx()
488 out0 = FILT_8TAP_DPADD_S_H(reg0, reg1, reg2, reg3, filter0, filter1, in common_vt_8t_4w_lsx()
490 out1 = FILT_8TAP_DPADD_S_H(reg1, reg2, reg3, reg4, filter0, filter1, in common_vt_8t_4w_lsx()
503 reg0 = reg2; in common_vt_8t_4w_lsx()
505 reg2 = reg4; in common_vt_8t_4w_lsx()
517 __m128i reg0, reg1, reg2, reg3, reg4, reg5; in common_vt_8t_8w_lsx() local
541 reg0, reg1, reg2, reg in common_vt_8t_8w_lsx()
589 __m128i reg0, reg1, reg2, reg3, reg4, reg5; common_vt_8t_16w_lsx() local
683 __m128i reg0, reg1, reg2, reg3, reg4, reg5; common_vt_8t_16w_mult_lsx() local
1543 __m128i reg0, reg1, reg2, reg3, reg4; common_vt_8t_and_aver_dst_4w_lsx() local
1619 __m128i reg0, reg1, reg2, reg3, reg4, reg5; common_vt_8t_and_aver_dst_8w_lsx() local
1705 __m128i reg0, reg1, reg2, reg3, reg4, reg5; common_vt_8t_and_aver_dst_16w_mult_lsx() local
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H A Dvp9_intra_lsx.c600 __m128i tmp0, tmp1, tmp2, tmp3, reg0, reg1, reg2; in ff_tm_32x32_lsx() local
605 DUP2_ARG2(__lsx_vld, src_top_ptr, 0, src_top_ptr, 16, reg1, reg2); in ff_tm_32x32_lsx()
620 DUP4_ARG2(__lsx_vaddwev_h_bu, tmp0, reg2, tmp1, reg2, tmp2, reg2, in ff_tm_32x32_lsx()
621 tmp3, reg2, dst0, dst1, dst2, dst3); in ff_tm_32x32_lsx()
622 DUP4_ARG2(__lsx_vaddwod_h_bu, tmp0, reg2, tmp1, reg2, tmp2, reg2, in ff_tm_32x32_lsx()
623 tmp3, reg2, dst in ff_tm_32x32_lsx()
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/third_party/backends/backend/genesys/
H A Dtables_frontend.cpp61 fe.reg2 = {0x00, 0x00, 0x00}; in genesys_init_frontend_tables()
83 fe.reg2 = {0x00, 0x00, 0x00}; in genesys_init_frontend_tables()
105 fe.reg2 = {0x00, 0x00, 0x00}; in genesys_init_frontend_tables()
127 fe.reg2 = {0x00, 0x00, 0x00}; in genesys_init_frontend_tables()
150 fe.reg2 = {0x00, 0x00, 0x00}; in genesys_init_frontend_tables()
172 fe.reg2 = {0x00, 0x00, 0x00}; in genesys_init_frontend_tables()
195 fe.reg2 = {0x00, 0x19, 0x06}; in genesys_init_frontend_tables()
219 fe.reg2 = {0x00, 0x00, 0x00}; in genesys_init_frontend_tables()
241 fe.reg2 = {0x00, 0x00, 0x00}; in genesys_init_frontend_tables()
264 fe.reg2 in genesys_init_frontend_tables()
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H A Dsensor.cpp85 << " reg2[0]: " << frontend.reg2[0] << '\n' in operator <<()
86 << " reg2[1]: " << frontend.reg2[1] << '\n' in operator <<()
87 << " reg2[2]: " << frontend.reg2[2] << '\n' in operator <<()
/third_party/mesa3d/src/gallium/drivers/r600/sfn/tests/
H A Dsfn_value_test.cpp58 Register reg2(3, 1, pin_fully); in TEST_F()
60 EXPECT_EQ(reg2.sel(), 3); in TEST_F()
61 EXPECT_EQ(reg2.chan(), 1); in TEST_F()
62 EXPECT_EQ(reg2.pin(), pin_fully); in TEST_F()
63 EXPECT_FALSE(reg2.is_virtual()); in TEST_F()
82 Register reg2(1025, 2, pin_none); in TEST_F()
84 EXPECT_EQ(reg2.sel(), 1025); in TEST_F()
85 EXPECT_EQ(reg2.chan(), 2); in TEST_F()
86 EXPECT_EQ(reg2.pin(), pin_none); in TEST_F()
87 EXPECT_TRUE(reg2 in TEST_F()
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/third_party/node/deps/openssl/openssl/crypto/aria/
H A Daria.c474 register uint32_t reg0, reg1, reg2, reg3; in ossl_aria_encrypt() local
491 reg2 = GET_U32_BE(in, 2); in ossl_aria_encrypt()
494 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
497 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
498 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
502 ARIA_SUBST_DIFF_EVEN(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
503 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
506 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
507 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
521 reg2 in ossl_aria_encrypt()
541 register uint32_t reg0, reg1, reg2, reg3; ossl_aria_set_encrypt_key() local
676 register uint32_t reg0, reg1, reg2, reg3; ossl_aria_set_decrypt_key() local
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/third_party/openssl/crypto/aria/
H A Daria.c474 register uint32_t reg0, reg1, reg2, reg3; in ossl_aria_encrypt() local
491 reg2 = GET_U32_BE(in, 2); in ossl_aria_encrypt()
494 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
497 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
498 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
502 ARIA_SUBST_DIFF_EVEN(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
503 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
506 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
507 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
521 reg2 in ossl_aria_encrypt()
541 register uint32_t reg0, reg1, reg2, reg3; ossl_aria_set_encrypt_key() local
676 register uint32_t reg0, reg1, reg2, reg3; ossl_aria_set_decrypt_key() local
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/third_party/node/deps/openssl/openssl/crypto/perlasm/
H A Dx86gas.pl77 { my($addr,$reg1,$reg2,$idx)=@_;
80 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
87 $reg2 = "%$reg2" if ($reg2);
91 if ($reg2)
93 $ret .= "($reg1,$reg2,$idx)";
H A Dx86nasm.pl43 { my($size,$addr,$reg1,$reg2,$idx)=@_;
46 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
66 if ($reg2 ne "")
68 $ret .= "$reg2*$idx";
H A Dx86masm.pl46 { my($size,$addr,$reg1,$reg2,$idx)=@_;
49 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
65 if ($reg2 ne "")
67 $ret .= "$reg2*$idx";
/third_party/openssl/crypto/perlasm/
H A Dx86gas.pl77 { my($addr,$reg1,$reg2,$idx)=@_;
80 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
87 $reg2 = "%$reg2" if ($reg2);
91 if ($reg2)
93 $ret .= "($reg1,$reg2,$idx)";
H A Dx86nasm.pl43 { my($size,$addr,$reg1,$reg2,$idx)=@_;
46 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
66 if ($reg2 ne "")
68 $ret .= "$reg2*$idx";
H A Dx86masm.pl46 { my($size,$addr,$reg1,$reg2,$idx)=@_;
49 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
65 if ($reg2 ne "")
67 $ret .= "$reg2*$idx";
/third_party/vixl/src/aarch64/
H A Dregisters-aarch64.h974 const CPURegister& reg2,
989 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
1030 const CPURegister& reg2,
1039 match &= !reg2.IsValid() || reg2.IsSameSizeAndType(reg1);
1054 const CPURegister& reg2,
1063 even &= !reg2.IsValid() || ((reg2.GetCode() % 2) == 0);
1079 const CPURegister& reg2,
1084 if (!reg2
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/third_party/ffmpeg/libavcodec/mips/
H A Dvp9_idct_msa.c967 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vp9_idct16_1d_columns_addblk_msa() local
974 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, in vp9_idct16_1d_columns_addblk_msa()
981 VP9_DOTP_CONST_PAIR(reg2, reg14, cospi_28_64, cospi_4_64, reg2, reg14); in vp9_idct16_1d_columns_addblk_msa()
983 BUTTERFLY_4(reg2, reg14, reg6, reg10, loc0, loc1, reg14, reg2); in vp9_idct16_1d_columns_addblk_msa()
984 VP9_DOTP_CONST_PAIR(reg14, reg2, cospi_16_64, cospi_16_64, loc2, loc3); in vp9_idct16_1d_columns_addblk_msa()
987 BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14); in vp9_idct16_1d_columns_addblk_msa()
989 reg0 = reg2 - loc1; in vp9_idct16_1d_columns_addblk_msa()
990 reg2 in vp9_idct16_1d_columns_addblk_msa()
1070 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; vp9_idct16_1d_columns_msa() local
1634 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; vp9_idct8x32_column_even_process_store() local
1718 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; vp9_idct8x32_column_odd_process_store() local
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/third_party/ffmpeg/libavutil/mips/
H A Dmmiutils.h130 #define MMI_LQ(reg1, reg2, addr, bias) \
132 "ld "#reg2", 8+"#bias"("#addr") \n\t"
134 #define MMI_SQ(reg1, reg2, addr, bias) \
136 "sd "#reg2", 8+"#bias"("#addr") \n\t"
216 #define MMI_LQ(reg1, reg2, addr, bias) \
217 "gslq "#reg1", "#reg2", "#bias"("#addr") \n\t"
219 #define MMI_SQ(reg1, reg2, addr, bias) \
220 "gssq "#reg1", "#reg2", "#bias"("#addr") \n\t"
/third_party/ffmpeg/libavcodec/aarch64/
H A Dvp9mc_16bpp_neon.S326 .macro do_store4 reg1, reg2, reg3, reg4, tmp1, tmp2, tmp3, tmp4, minreg, type
328 sqrshrun \reg2\().4h, \reg2\().4s, #7
338 umin \reg2\().4h, \reg2\().4h, \minreg\().4h
343 urhadd \reg2\().4h, \reg2\().4h, \tmp2\().4h
348 st1 {\reg2\().4h}, [x0], x1
355 .macro do_store8 reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, minreg, type
357 sqrshrun2 \reg1\().8h, \reg2\()
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H A Dvp9mc_neon.S388 // Round, shift and saturate and store reg1-reg2 over 4 lines
389 .macro do_store4 reg1, reg2, tmp1, tmp2, type
391 sqrshrun \reg2\().8b, \reg2\().8h, #7
398 urhadd \reg2\().8b, \reg2\().8b, \tmp2\().8b
401 st1 {\reg2\().s}[0], [x0], x1
403 st1 {\reg2\().s}[1], [x0], x1
407 .macro do_store reg1, reg2, reg3, reg4, tmp1, tmp2, tmp3, tmp4, type
409 sqrshrun \reg2\()
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/third_party/node/deps/v8/src/interpreter/
H A Dbytecode-register.cc105 bool Register::AreContiguous(Register reg1, Register reg2, Register reg3, in AreContiguous() argument
107 if (reg1.index() + 1 != reg2.index()) { in AreContiguous()
110 if (reg3.is_valid() && reg2.index() + 1 != reg3.index()) { in AreContiguous()
/third_party/ffmpeg/tests/checkasm/aarch64/
H A Dcheckasm.S151 .macro check_reg_neon reg1, reg2
153 uzp1 v2.2d, v\reg1\().2d, v\reg2\().2d
164 .macro check_reg reg1, reg2
167 eor x1, x1, \reg2
/third_party/mesa3d/src/panfrost/bifrost/
H A Ddisassemble.c152 else if (regs.reg2 == regs.reg3) in DecodeRegCtrl()
174 fprintf(fp, "slot 2: r%u (write FMA) ", srcs.reg2); in dump_regs()
176 fprintf(fp, "slot 2: r%u (write lo FMA) ", srcs.reg2); in dump_regs()
178 fprintf(fp, "slot 2: r%u (write hi FMA) ", srcs.reg2); in dump_regs()
180 fprintf(fp, "slot 2: r%u (read) ", srcs.reg2); in dump_regs()
210 fprintf(fp, "r%u:t0", next_regs->reg2); in bi_disasm_dest_fma()
375 fprintf(fp, "r%u", srcs.reg2); in dump_src()
/third_party/ffmpeg/tests/checkasm/arm/
H A Dcheckasm.S147 .macro check_reg reg1, reg2=
152 .ifnb \reg2
153 eors r3, r3, \reg2
/third_party/backends/backend/
H A Dp5_device.c724 uint8_t reg2=0; in start_scan() local
735 * - reg2 : reg2 seems related to x dpi and provides only 100, in start_scan()
744 reg2 = 0x90; in start_scan()
748 reg2 = 0x10; in start_scan()
752 reg2 = 0x80; in start_scan()
756 reg2 = 0x00; in start_scan()
760 reg2 = 0x80; /* xdpi=200 */ in start_scan()
765 reg2 = 0x00; in start_scan()
770 reg2 in start_scan()
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