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Searched refs:radeon_set_sh_reg_seq (Results 1 - 10 of 10) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_compute.c382 radeon_set_sh_reg_seq(R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2); in si_emit_initial_compute_regs()
402 radeon_set_sh_reg_seq(R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2); in si_emit_initial_compute_regs()
433 radeon_set_sh_reg_seq(R_00B894_COMPUTE_STATIC_THREAD_MGMT_SE4, 4); in si_emit_initial_compute_regs()
441 radeon_set_sh_reg_seq(R_00B890_COMPUTE_USER_ACCUM_0, 4); in si_emit_initial_compute_regs()
454 radeon_set_sh_reg_seq(R_00B8AC_COMPUTE_STATIC_THREAD_MGMT_SE4, 4); in si_emit_initial_compute_regs()
574 radeon_set_sh_reg_seq(R_00B840_COMPUTE_DISPATCH_SCRATCH_BASE_LO, 4); in si_switch_compute_shader()
578 radeon_set_sh_reg_seq(R_00B848_COMPUTE_PGM_RSRC1, 2); in si_switch_compute_shader()
633 radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 4); in setup_scratch_rsrc_user_sgprs()
697 radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 2); in si_setup_user_sgprs_co_v2()
707 radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_ in si_setup_user_sgprs_co_v2()
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H A Dsi_build_pm4.h113 #define radeon_set_sh_reg_seq(reg, num) do { \ macro
128 radeon_set_sh_reg_seq(reg, 1); \
303 radeon_set_sh_reg_seq(sh_offset, 1); \
H A Dsi_state_draw.cpp817 radeon_set_sh_reg_seq(
832 radeon_set_sh_reg_seq(R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
837 radeon_set_sh_reg_seq(
846 radeon_set_sh_reg_seq(tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
1635 radeon_set_sh_reg_seq(sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4, sctx->num_vs_blit_sgprs);
1647 radeon_set_sh_reg_seq(sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
1655 radeon_set_sh_reg_seq(sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2);
1697 radeon_set_sh_reg_seq(sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2);
1780 radeon_set_sh_reg_seq(sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2);
1951 radeon_set_sh_reg_seq(sh_bas
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H A Dsi_descriptors.c2167 radeon_set_sh_reg_seq(sh_offset, count); \
2273 radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_0 + in si_emit_compute_shader_pointers()
2288 radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_0 + in si_emit_compute_shader_pointers()
/third_party/mesa3d/src/gallium/drivers/r600/
H A Dr600_cs.h167 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_sh_reg_seq() function
177 radeon_set_sh_reg_seq(cs, reg, 1); in radeon_set_sh_reg()
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_cs.h98 radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_sh_reg_seq() function
110 radeon_set_sh_reg_seq(cs, reg, 1); in radeon_set_sh_reg()
H A Dsi_cmd_buffer.c79 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3); in si_emit_compute()
87 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2); in si_emit_compute()
95 radeon_set_sh_reg_seq(cs, R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2); in si_emit_compute()
115 radeon_set_sh_reg_seq(cs, R_00B890_COMPUTE_USER_ACCUM_0, 5); in si_emit_compute()
148 radeon_set_sh_reg_seq(cs, R_00B838_COMPUTE_TBA_LO, 4); in si_emit_compute()
158 radeon_set_sh_reg_seq(cs, R_00B8AC_COMPUTE_STATIC_THREAD_MGMT_SE4, 4); in si_emit_compute()
467 radeon_set_sh_reg_seq(cs, R_00B0C8_SPI_SHADER_USER_ACCUM_PS_0, 4); in si_emit_graphics()
474 radeon_set_sh_reg_seq(cs, R_00B1C8_SPI_SHADER_USER_ACCUM_VS_0, 4); in si_emit_graphics()
481 radeon_set_sh_reg_seq(cs, R_00B2C8_SPI_SHADER_USER_ACCUM_ESGS_0, 4); in si_emit_graphics()
486 radeon_set_sh_reg_seq(c in si_emit_graphics()
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H A Dradv_pipeline.c5653 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4); in radv_pipeline_emit_hw_vs()
5731 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4); in radv_pipeline_emit_hw_es()
5753 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2); in radv_pipeline_emit_hw_ls()
5773 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2); in radv_pipeline_emit_hw_ngg()
5951 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2); in radv_pipeline_emit_hw_hs()
5955 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4); in radv_pipeline_emit_hw_hs()
6146 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2); in radv_pipeline_emit_hw_gs()
6154 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4); in radv_pipeline_emit_hw_gs()
6398 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4); in radv_pipeline_emit_fragment_shader()
7175 radeon_set_sh_reg_seq(c in radv_pipeline_emit_hw_cs()
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H A Dradv_cmd_buffer.c1217 radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, loc->num_sgprs); in radv_emit_inline_push_consts()
6843 radeon_set_sh_reg_seq(cs, state->graphics_pipeline->vtx_base_sgpr, state->graphics_pipeline->vtx_emit_num); in radv_emit_userdata_vertex_internal()
6882 radeon_set_sh_reg_seq(cs, state->graphics_pipeline->vtx_base_sgpr, 1 + !!drawid); in radv_emit_userdata_vertex_drawid()
6899 radeon_set_sh_reg_seq(cs, state->graphics_pipeline->vtx_base_sgpr, state->graphics_pipeline->vtx_emit_num); in radv_emit_userdata_mesh()
6919 radeon_set_sh_reg_seq(cs, pipeline->vtx_base_sgpr, 1); in radv_emit_userdata_mesh_first_task_0_draw_id_0()
6923 radeon_set_sh_reg_seq(cs, pipeline->vtx_base_sgpr + (pipeline->vtx_emit_num - 1) * 4, 1); in radv_emit_userdata_mesh_first_task_0_draw_id_0()
6942 radeon_set_sh_reg_seq(cs, task_ib_reg, 3); in radv_emit_userdata_task_ib_only()
6965 radeon_set_sh_reg_seq(cs, xyz_reg, 3); in radv_emit_userdata_task()
6975 radeon_set_sh_reg_seq(cs, draw_id_reg, 1); in radv_emit_userdata_task()
7549 radeon_set_sh_reg_seq(cmd_buffe in radv_emit_ngg_culling_state()
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H A Dradv_device.c4250 radeon_set_sh_reg_seq(cs, R_00B840_COMPUTE_DISPATCH_SCRATCH_BASE_LO, 2); in radv_emit_compute_scratch()
4257 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2); in radv_emit_compute_scratch()

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