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Searched refs:radeon_set_sh_reg (Results 1 - 15 of 15) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_compute.c379 radeon_set_sh_reg(R_00B834_COMPUTE_PGM_HI, in si_emit_initial_compute_regs()
396 radeon_set_sh_reg(R_00B82C_COMPUTE_MAX_WAVE_ID, 0x190 /* Default value */); in si_emit_initial_compute_regs()
408 radeon_set_sh_reg(R_00B82C_COMPUTE_PERFCOUNT_ENABLE, 0); in si_emit_initial_compute_regs()
409 radeon_set_sh_reg(R_00B878_COMPUTE_THREAD_TRACE_ENABLE, 0); in si_emit_initial_compute_regs()
447 radeon_set_sh_reg(R_00B9F4_COMPUTE_DISPATCH_TUNNEL, 0); in si_emit_initial_compute_regs()
450 radeon_set_sh_reg(R_00B8A0_COMPUTE_PGM_RSRC3, 0); in si_emit_initial_compute_regs()
460 radeon_set_sh_reg(R_00B8BC_COMPUTE_DISPATCH_INTERLEAVE, 64); in si_emit_initial_compute_regs()
566 radeon_set_sh_reg(R_00B830_COMPUTE_PGM_LO, shader_va >> 8); in si_switch_compute_shader()
569 radeon_set_sh_reg(R_00B8A0_COMPUTE_PGM_RSRC3, in si_switch_compute_shader()
589 radeon_set_sh_reg(R_00B860_COMPUTE_TMPRING_SIZ in si_switch_compute_shader()
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H A Dsi_build_pm4.h127 #define radeon_set_sh_reg(reg, value) do { \ macro
256 radeon_set_sh_reg(offset, __value); \
269 radeon_set_sh_reg(offset, __value); \
312 radeon_set_sh_reg(reg_offset, value); in radeon_set_sh_reg_func()
H A Dsi_state_draw.cpp814 radeon_set_sh_reg(R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
831 radeon_set_sh_reg(R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
1238 radeon_set_sh_reg(vs_base + SI_SGPR_VS_STATE_BITS * 4, vs_state);
1244 radeon_set_sh_reg(gs_base + SI_SGPR_VS_STATE_BITS * 4, gs_state);
1248 radeon_set_sh_reg(gs_copy_base + SI_SGPR_VS_STATE_BITS * 4, gs_state);
1250 radeon_set_sh_reg(vs_base + SI_SGPR_VS_STATE_BITS * 4, vs_state);
1251 radeon_set_sh_reg(tes_base + SI_SGPR_VS_STATE_BITS * 4, NGG ? gs_state : vs_state);
1253 radeon_set_sh_reg(vs_base + SI_SGPR_VS_STATE_BITS * 4, NGG ? gs_state : vs_state);
1661 radeon_set_sh_reg(sh_base_reg + SI_SGPR_BASE_VERTEX * 4, base_vertex);
1719 radeon_set_sh_reg(sh_base_re
[all...]
H A Dsi_perfcounter.c181 radeon_set_sh_reg(R_00B82C_COMPUTE_PERFCOUNT_ENABLE, S_00B82C_PERFCOUNT_ENABLE(1)); in si_pc_emit_spm_start()
197 radeon_set_sh_reg(R_00B82C_COMPUTE_PERFCOUNT_ENABLE, S_00B82C_PERFCOUNT_ENABLE(0)); in si_pc_emit_spm_stop()
H A Dsi_sqtt.c220 radeon_set_sh_reg(R_00B878_COMPUTE_THREAD_TRACE_ENABLE, in si_emit_thread_trace_start()
295 radeon_set_sh_reg(R_00B878_COMPUTE_THREAD_TRACE_ENABLE, in si_emit_thread_trace_stop()
H A Dsi_state_viewport.c112 radeon_set_sh_reg(R_00B230_SPI_SHADER_USER_DATA_GS_0 + GFX9_SGPR_SMALL_PRIM_CULL_INFO * 4, in si_emit_cull_state()
H A Dsi_descriptors.c2238 radeon_set_sh_reg(R_00B230_SPI_SHADER_USER_DATA_GS_0 + GFX9_SGPR_ATTRIBUTE_RING_ADDR * 4, in si_emit_graphics_shader_pointers()
/third_party/mesa3d/src/amd/vulkan/
H A Dsi_cmd_buffer.c84 radeon_set_sh_reg(cs, R_00B834_COMPUTE_PGM_HI, in si_emit_compute()
132 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID, 0x190 /* Default value */); in si_emit_compute()
164 radeon_set_sh_reg(cs, R_00B8BC_COMPUTE_DISPATCH_INTERLEAVE, 64); in si_emit_compute()
318 radeon_set_sh_reg(cs, R_00B524_SPI_SHADER_PGM_HI_LS, in si_emit_graphics()
320 radeon_set_sh_reg(cs, R_00B324_SPI_SHADER_PGM_HI_ES, in si_emit_graphics()
323 radeon_set_sh_reg(cs, R_00B414_SPI_SHADER_PGM_HI_LS, in si_emit_graphics()
325 radeon_set_sh_reg(cs, R_00B214_SPI_SHADER_PGM_HI_ES, in si_emit_graphics()
328 radeon_set_sh_reg(cs, R_00B524_SPI_SHADER_PGM_HI_LS, in si_emit_graphics()
330 radeon_set_sh_reg(cs, R_00B324_SPI_SHADER_PGM_HI_ES, in si_emit_graphics()
335 radeon_set_sh_reg(c in si_emit_graphics()
[all...]
H A Dradv_cs.h108 radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_sh_reg() function
H A Dradv_sqtt.c199 radeon_set_sh_reg(cs, R_00B878_COMPUTE_THREAD_TRACE_ENABLE, S_00B878_THREAD_TRACE_ENABLE(1)); in radv_emit_thread_trace_start()
263 radeon_set_sh_reg(cs, R_00B878_COMPUTE_THREAD_TRACE_ENABLE, S_00B878_THREAD_TRACE_ENABLE(0)); in radv_emit_thread_trace_stop()
H A Dradv_pipeline.c5717 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(late_alloc_wave64)); in radv_pipeline_emit_hw_vs()
5747 radeon_set_sh_reg(cs, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8); in radv_pipeline_emit_hw_ls()
5751 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2); in radv_pipeline_emit_hw_ls()
5771 radeon_set_sh_reg(cs, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8); in radv_pipeline_emit_hw_ngg()
5946 radeon_set_sh_reg(cs, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8); in radv_pipeline_emit_hw_hs()
5948 radeon_set_sh_reg(cs, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8); in radv_pipeline_emit_hw_hs()
6141 radeon_set_sh_reg(cs, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8); in radv_pipeline_emit_hw_gs()
6143 radeon_set_sh_reg(cs, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8); in radv_pipeline_emit_hw_gs()
7173 radeon_set_sh_reg(cs, R_00B830_COMPUTE_PGM_LO, va >> 8); in radv_pipeline_emit_hw_cs()
7179 radeon_set_sh_reg(c in radv_pipeline_emit_hw_cs()
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H A Dradv_cmd_buffer.c1581 radeon_set_sh_reg(cmd_buffer->cs, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, in radv_emit_graphics_pipeline()
3246 radeon_set_sh_reg(cmd_buffer->cs, pgm_lo_reg, prolog_va >> 8); in emit_prolog_regs()
3249 radeon_set_sh_reg(cmd_buffer->cs, rsrc1_reg, rsrc1); in emit_prolog_regs()
4013 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, ngg_query_state); in radv_flush_ngg_query_state()
4053 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, vrs_rates); in radv_flush_force_vrs_state()
6565 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, index); in radv_emit_view_index_per_stage()
6581 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index); in radv_emit_view_index()
7010 radeon_set_sh_reg(cs, state->graphics_pipeline->vtx_base_sgpr + sizeof(uint32_t), i); in radv_emit_draw_packets_indexed()
7037 radeon_set_sh_reg(cs, state->graphics_pipeline->vtx_base_sgpr + sizeof(uint32_t), i); in radv_emit_draw_packets_indexed()
7562 radeon_set_sh_reg(cmd_buffe in radv_emit_ngg_culling_state()
[all...]
H A Dradv_perfcounter.c50 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_PERFCOUNT_ENABLE, S_00B82C_PERFCOUNT_ENABLE(enable)); in radv_emit_windowed_counters()
H A Dradv_device.c4261 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE, in radv_emit_compute_scratch()
/third_party/mesa3d/src/gallium/drivers/r600/
H A Dr600_cs.h175 static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_sh_reg() function

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