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/third_party/vixl/test/aarch32/
H A Dtest-assembler-cond-rdlow-rnlow-rmlow-in-it-block-t32.cc100 {{eq, r0, r5, r0}, true, eq, "eq r0 r5 r0", "eq_r0_r5_r0"},
108 {{eq, r1, r5, r1}, true, eq, "eq r1 r5 r1", "eq_r1_r5_r1"},
116 {{eq, r2, r5, r2}, true, eq, "eq r2 r5 r2", "eq_r2_r5_r2"},
124 {{eq, r3, r5, r3}, true, eq, "eq r3 r5 r3", "eq_r3_r5_r3"},
132 {{eq, r4, r5, r4}, true, eq, "eq r4 r5 r
[all...]
H A Dtest-assembler-cond-rd-operand-rn-low-registers-in-it-block-t32.cc100 {{eq, r0, r5}, true, eq, "eq r0 r5", "eq_r0_r5"},
108 {{eq, r1, r5}, true, eq, "eq r1 r5", "eq_r1_r5"},
116 {{eq, r2, r5}, true, eq, "eq r2 r5", "eq_r2_r5"},
124 {{eq, r3, r5}, true, eq, "eq r3 r5", "eq_r3_r5"},
132 {{eq, r4, r5}, true, eq, "eq r4 r5", "eq_r4_r
[all...]
H A Dtest-assembler-cond-rdlow-rnlow-operand-immediate-zero-in-it-block-t32.cc100 {{eq, r0, r5, 0}, true, eq, "eq r0 r5 0", "eq_r0_r5_0"},
108 {{eq, r1, r5, 0}, true, eq, "eq r1 r5 0", "eq_r1_r5_0"},
116 {{eq, r2, r5, 0}, true, eq, "eq r2 r5 0", "eq_r2_r5_0"},
124 {{eq, r3, r5, 0}, true, eq, "eq r3 r5 0", "eq_r3_r5_0"},
132 {{eq, r4, r5, 0}, true, eq, "eq r4 r5
[all...]
H A Dtest-assembler-cond-rdlow-rnlow-operand-immediate-imm8-t32.cc1377 {{al, r5, r5, 0}, false, al, "al r5 r5 0", "al_r5_r5_0"},
1378 {{al, r5, r5, 1}, false, al, "al r5 r5 1", "al_r5_r5_1"},
1379 {{al, r5, r5,
[all...]
H A Dtest-assembler-cond-rd-operand-rn-shift-amount-1to31-in-it-block-t32.cc98 {{lt, r5, r3, LSL, 21}, true, lt, "lt r5 r3 LSL 21", "lt_r5_r3_LSL_21"},
99 {{ge, r5, r0, LSL, 3}, true, ge, "ge r5 r0 LSL 3", "ge_r5_r0_LSL_3"},
111 {{gt, r5, r3, LSL, 1}, true, gt, "gt r5 r3 LSL 1", "gt_r5_r3_LSL_1"},
115 {{le, r5, r2, LSL, 1}, true, le, "le r5 r2 LSL 1", "le_r5_r2_LSL_1"},
118 {{le, r5, r4, LSL, 6}, true, le, "le r5 r
[all...]
H A Dtest-assembler-cond-rd-operand-rn-shift-rs-in-it-block-t32.cc104 {{hi, r6, r6, ROR, r5}, true, hi, "hi r6 r6 ROR r5", "hi_r6_r6_ROR_r5"},
108 {{mi, r4, r4, LSL, r5}, true, mi, "mi r4 r4 LSL r5", "mi_r4_r4_LSL_r5"},
109 {{le, r5, r5, LSR, r6}, true, le, "le r5 r5 LSR r6", "le_r5_r5_LSR_r6"},
112 {{hi, r5, r5, LS
[all...]
H A Dtest-assembler-cond-rdlow-rnlow-operand-immediate-imm8-in-it-block-t32.cc99 {{cc, r5, r5, 72}, true, cc, "cc r5 r5 72", "cc_r5_r5_72"},
102 {{vc, r5, r5, 114}, true, vc, "vc r5 r5 114", "vc_r5_r5_114"},
107 {{vs, r5, r5, 19
[all...]
H A Dtest-assembler-cond-rd-operand-rn-shift-rs-narrow-out-it-block-t32.cc101 {{al, r0, r0, LSL, r5}, false, al, "al r0 r0 LSL r5", "al_r0_r0_LSL_r5"},
109 {{al, r0, r0, LSR, r5}, false, al, "al r0 r0 LSR r5", "al_r0_r0_LSR_r5"},
117 {{al, r0, r0, ASR, r5}, false, al, "al r0 r0 ASR r5", "al_r0_r0_ASR_r5"},
125 {{al, r0, r0, ROR, r5}, false, al, "al r0 r0 ROR r5", "al_r0_r0_ROR_r5"},
133 {{al, r1, r1, LSL, r5}, false, al, "al r1 r1 LSL r5", "al_r1_r1_LSL_r
[all...]
H A Dtest-assembler-cond-rdlow-rnlow-operand-immediate-imm3-in-it-block-t32.cc100 {{cc, r5, r1, 6}, true, cc, "cc r5 r1 6", "cc_r5_r1_6"},
101 {{cs, r5, r2, 0}, true, cs, "cs r5 r2 0", "cs_r5_r2_0"},
102 {{vs, r5, r6, 7}, true, vs, "vs r5 r6 7", "vs_r5_r6_7"},
105 {{lt, r4, r5, 7}, true, lt, "lt r4 r5 7", "lt_r4_r5_7"},
109 {{vc, r5, r2, 5}, true, vc, "vc r5 r
[all...]
H A Dtest-assembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-t32.cc109 {{eq, r5, r5, r2}, true, eq, "eq r5 r5 r2", "eq_r5_r5_r2"},
114 {{eq, r5, r5, r5}, true, eq, "eq r5 r5 r5", "eq_r5_r5_r
[all...]
H A Dtest-assembler-cond-rdlow-rnlow-operand-immediate-imm3-t32.cc137 {{al, r0, r5, 0}, false, al, "al r0 r5 0", "al_r0_r5_0"},
138 {{al, r0, r5, 1}, false, al, "al r0 r5 1", "al_r0_r5_1"},
139 {{al, r0, r5, 2}, false, al, "al r0 r5 2", "al_r0_r5_2"},
140 {{al, r0, r5, 3}, false, al, "al r0 r5 3", "al_r0_r5_3"},
141 {{al, r0, r5, 4}, false, al, "al r0 r5
[all...]
H A Dtest-assembler-cond-rd-rn-operand-rm-all-low-in-it-block-t32.cc97 {{{cs, r7, r1, r5}, true, cs, "cs r7 r1 r5", "cs_r7_r1_r5"},
100 {{pl, r5, r3, r4}, true, pl, "pl r5 r3 r4", "pl_r5_r3_r4"},
107 {{ne, r5, r1, r0}, true, ne, "ne r5 r1 r0", "ne_r5_r1_r0"},
114 {{le, r5, r5, r4}, true, le, "le r5 r5 r
[all...]
/third_party/ffmpeg/libavcodec/x86/
H A Dqpeldsp.asm405 mov r5, rsp
416 mova [r5], m0
417 mova [r5+0x88], m1
418 mova [r5+0x110], m2
419 mova [r5+0x198], m3
420 add r5, 8
434 mov r5, rsp
437 mova m0, [r5+ 0x0]
438 mova m1, [r5+ 0x8]
439 mova m2, [r5
[all...]
/third_party/musl/src/setjmp/microblaze/
H A Dsetjmp.s13 swi r1, r5, 0
14 swi r15, r5, 4
15 swi r2, r5, 8
16 swi r13, r5, 12
17 swi r18, r5, 16
18 swi r19, r5, 20
19 swi r20, r5, 24
20 swi r21, r5, 28
21 swi r22, r5, 32
22 swi r23, r5, 3
[all...]
H A Dlongjmp.s10 1: lwi r1, r5, 0
11 lwi r15, r5, 4
12 lwi r2, r5, 8
13 lwi r13, r5, 12
14 lwi r18, r5, 16
15 lwi r19, r5, 20
16 lwi r20, r5, 24
17 lwi r21, r5, 28
18 lwi r22, r5, 32
19 lwi r23, r5, 3
[all...]
/third_party/ffmpeg/libavcodec/arm/
H A Dsbcdsp_armv6.S38 ldrd r4, r5, [r0, #0]
44 smlad r12, r5, r7, r14
45 ldrd r4, r5, [r0, #32]
52 smlad r12, r5, r7, r12
53 ldrd r4, r5, [r0, #64]
60 smlad r12, r5, r7, r12 @ t1[1] is done
61 ldrd r4, r5, [r0, #24]
69 smlad r14, r5, r7, r14
70 ldrd r4, r5, [r0, #56]
77 smlad r14, r5, r
[all...]
H A Dhpeldsp_arm.S97 JMP_ALIGN r5, r1
111 ALIGN_QWORD_D 1, r9, r10, r11, r12, r4, r5, r6, r7, r8
122 ALIGN_QWORD_D 2, r9, r10, r11, r12, r4, r5, r6, r7, r8
133 ALIGN_QWORD_D 3, r9, r10, r11, r12, r4, r5, r6, r7, r8
147 push {r4-r5,lr}
148 JMP_ALIGN r5, r1
150 ldm r1, {r4-r5}
154 stm r0, {r4-r5}
157 pop {r4-r5,pc}
160 ldm r1, {r4-r5, r1
[all...]
/third_party/node/deps/openssl/config/archs/linux32-s390x/asm_avx2/crypto/sha/
H A Dsha1-s390x.S33 llgf %r5,0(%r2)
48 rll %r11,%r5,5
62 nr %r10,%r5
65 rll %r5,%r5,30
73 xr %r10,%r5
82 lr %r10,%r5
87 xr %r10,%r5
93 alr %r5,%r0 ### 4
97 alr %r5,
[all...]
/third_party/node/deps/openssl/config/archs/linux32-s390x/asm/crypto/sha/
H A Dsha1-s390x.S33 llgf %r5,0(%r2)
48 rll %r11,%r5,5
62 nr %r10,%r5
65 rll %r5,%r5,30
73 xr %r10,%r5
82 lr %r10,%r5
87 xr %r10,%r5
93 alr %r5,%r0 ### 4
97 alr %r5,
[all...]
/third_party/node/deps/openssl/config/archs/linux64-s390x/asm/crypto/sha/
H A Dsha1-s390x.S33 llgf %r5,0(%r2)
48 rll %r11,%r5,5
62 nr %r10,%r5
65 rll %r5,%r5,30
73 xr %r10,%r5
82 lr %r10,%r5
87 xr %r10,%r5
93 alr %r5,%r0 ### 4
97 alr %r5,
[all...]
/third_party/node/deps/openssl/config/archs/linux64-s390x/asm_avx2/crypto/sha/
H A Dsha1-s390x.S33 llgf %r5,0(%r2)
48 rll %r11,%r5,5
62 nr %r10,%r5
65 rll %r5,%r5,30
73 xr %r10,%r5
82 lr %r10,%r5
87 xr %r10,%r5
93 alr %r5,%r0 ### 4
97 alr %r5,
[all...]
/third_party/musl/src/string/arm/
H A Dmemcpy.S58 /* Making room for r5-r11 which will be spilled later */
93 /* Use post-incriment mode for stm to spill r5-r11 to reserved stack
96 stmea sp, {r5-r11}
107 ldmcs r1!, {r4, r5, r6, r7} /* 16 bytes */
109 stmcs r0!, {r4, r5, r6, r7}
177 ldmcs r1!, {r4, r5, r6, r7} /* 16 bytes */
179 stmcs r0!, {r4, r5, r6, r7}
191 1: ldmfd sp!, {r5-r11}
209 /* Use post-incriment mode for stm to spill r5-r11 to reserved stack
212 stmea sp, {r5
[all...]
/third_party/node/deps/openssl/config/archs/linux-armv4/asm/crypto/sha/
H A Dsha1-armv4-large.S32 stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
34 ldmia r0,{r3,r4,r5,r6,r7}
39 mov r5,r5,ror#30
50 eor r10,r5,r6 @ F_xx_xx
57 eor r10,r5,r6 @ F_xx_xx
75 eor r10,r4,r5 @ F_xx_xx
82 eor r10,r4,r5 @ F_xx_xx
90 eor r10,r10,r5,ror#2 @ F_00_19(B,C,D)
97 add r5,r
[all...]
/third_party/node/deps/openssl/config/archs/linux-armv4/asm_avx2/crypto/sha/
H A Dsha1-armv4-large.S32 stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
34 ldmia r0,{r3,r4,r5,r6,r7}
39 mov r5,r5,ror#30
50 eor r10,r5,r6 @ F_xx_xx
57 eor r10,r5,r6 @ F_xx_xx
75 eor r10,r4,r5 @ F_xx_xx
82 eor r10,r4,r5 @ F_xx_xx
90 eor r10,r10,r5,ror#2 @ F_00_19(B,C,D)
97 add r5,r
[all...]
/third_party/node/deps/openssl/openssl/crypto/bn/asm/
H A Dppc.pl235 #.set r5,5 # 3rd argument/volatile register
283 # Freely use registers r5,r6,r7,r8,r9,r10,r11 as follows:
285 # r5,r6 are the two BN_ULONGs being multiplied.
295 $LD r5,`0*$BNSZ`(r4)
296 $UMULL r9,r5,r5
297 $UMULH r10,r5,r5 #in first iteration. No need
305 $UMULL r7,r5,r6
306 $UMULH r8,r5,r
[all...]

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