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Searched refs:pow2Pad (Results 1 - 4 of 4) sorted by relevance

/third_party/mesa3d/src/amd/addrlib/src/r800/
H A Dsiaddrlib.cpp1749 // From SI, if pow2Pad is 1 the pitch is expanded 3x first, then padded to pow2, so nothing to
1751 if (pIn->flags.pow2Pad == FALSE)
1784 if (pIn->flags.pow2Pad == FALSE) in HwlPostHandleBaseLvl3xPitch()
2743 // we explicity set pow2Pad flag. The 3x base pitch is padded to pow2 but after being in HwlComputeMipLevel()
2748 // If pow2Pad is 0, we don't assert - as this is not really used for a mip chain in HwlComputeMipLevel()
2749 ADDR_ASSERT((pIn->flags.pow2Pad == FALSE) || in HwlComputeMipLevel()
2759 // pow2Pad is done in PostComputeMipLevel in HwlComputeMipLevel()
2779 // pow2Pad covers all mipmap cases in HwlCheckLastMacroTiledLvl()
2780 if (pIn->flags.pow2Pad) in HwlCheckLastMacroTiledLvl()
/third_party/mesa3d/src/amd/addrlib/inc/
H A Daddrinterface.h506 UINT_32 pow2Pad : 1; ///< SI: Pad to pow2, must set for mipmap (include level0) member
/third_party/mesa3d/src/amd/addrlib/src/core/
H A Daddrlib1.cpp3843 if (pIn->flags.pow2Pad) in PostComputeMipLevel()
/third_party/mesa3d/src/amd/common/
H A Dac_surface.c1112 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1; in gfx6_compute_surface()

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