| /third_party/mesa3d/src/amd/common/ |
| H A D | ac_surface_meta_address_test.c | 67 unsigned sample, unsigned pipe_xor, in gfx9_meta_addr_from_coord()
115 unsigned pipeXor = pipe_xor & ((1 << numPipeBits) - 1); in gfx9_meta_addr_from_coord()
128 unsigned pipe_xor, in gfx10_meta_addr_from_coord()
162 unsigned pipeXor = ((pipe_xor & pipeMask) << m_pipeInterleaveLog2) & blkMask; in gfx10_meta_addr_from_coord()
181 unsigned pipe_xor) in gfx10_dcc_addr_from_coord()
192 x, y, z, pipe_xor, NULL); in gfx10_dcc_addr_from_coord()
407 unsigned pipe_xor) in gfx10_htile_addr_from_coord()
417 x, y, z, pipe_xor, NULL); in gfx10_htile_addr_from_coord()
560 unsigned pipe_xor, in gfx10_cmask_addr_from_coord()
573 x, y, z, pipe_xor, bit_positio in gfx10_cmask_addr_from_coord()
57 gfx9_meta_addr_from_coord(const struct radeon_info *info, const struct gfx9_addr_meta_equation *eq, unsigned meta_block_width, unsigned meta_block_height, unsigned meta_block_depth, unsigned meta_pitch, unsigned meta_height, unsigned x, unsigned y, unsigned z, unsigned sample, unsigned pipe_xor, unsigned *bit_position) gfx9_meta_addr_from_coord() argument
120 gfx10_meta_addr_from_coord(const struct radeon_info *info, const uint16_t *equation, unsigned meta_block_width, unsigned meta_block_height, unsigned blkSizeLog2, unsigned meta_pitch, unsigned meta_slice_size, unsigned x, unsigned y, unsigned z, unsigned pipe_xor, unsigned *bit_position) gfx10_meta_addr_from_coord() argument
173 gfx10_dcc_addr_from_coord(const struct radeon_info *info, const uint16_t *equation, unsigned bpp, unsigned meta_block_width, unsigned meta_block_height, unsigned dcc_pitch, unsigned dcc_slice_size, unsigned x, unsigned y, unsigned z, unsigned pipe_xor) gfx10_dcc_addr_from_coord() argument
401 gfx10_htile_addr_from_coord(const struct radeon_info *info, const uint16_t *equation, unsigned meta_block_width, unsigned meta_block_height, unsigned htile_pitch, unsigned htile_slice_size, unsigned x, unsigned y, unsigned z, unsigned pipe_xor) gfx10_htile_addr_from_coord() argument
552 gfx10_cmask_addr_from_coord(const struct radeon_info *info, const uint16_t *equation, unsigned bpp, unsigned meta_block_width, unsigned meta_block_height, unsigned cmask_pitch, unsigned cmask_slice_size, unsigned x, unsigned y, unsigned z, unsigned pipe_xor, unsigned *bit_position) gfx10_cmask_addr_from_coord() argument
[all...] |
| H A D | ac_surface.h | 485 nir_ssa_def *sample, nir_ssa_def *pipe_xor);
492 nir_ssa_def *pipe_xor,
500 nir_ssa_def *pipe_xor);
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| H A D | ac_surface.c | 3128 nir_ssa_def *pipe_xor, in gfx10_nir_meta_addr_from_coord()
3167 nir_ssa_def *pipeXor = nir_iand_imm(b, nir_ishl(b, nir_iand_imm(b, pipe_xor, pipeMask), in gfx10_nir_meta_addr_from_coord()
3183 nir_ssa_def *sample, nir_ssa_def *pipe_xor, in gfx9_nir_meta_addr_from_coord()
3242 nir_ssa_def *pipeXor = nir_iand_imm(b, pipe_xor, (1 << numPipeBits) - 1); in gfx9_nir_meta_addr_from_coord()
3252 nir_ssa_def *sample, nir_ssa_def *pipe_xor) in ac_nir_dcc_addr_from_coord()
3259 x, y, z, pipe_xor, NULL); in ac_nir_dcc_addr_from_coord()
3263 sample, pipe_xor, NULL); in ac_nir_dcc_addr_from_coord()
3272 nir_ssa_def *pipe_xor, in ac_nir_cmask_addr_from_coord()
3280 x, y, z, pipe_xor, bit_position); in ac_nir_cmask_addr_from_coord()
3284 pipe_xor, bit_positio in ac_nir_cmask_addr_from_coord()
3123 gfx10_nir_meta_addr_from_coord(nir_builder *b, const struct radeon_info *info, struct gfx9_meta_equation *equation, int blkSizeBias, unsigned blkStart, nir_ssa_def *meta_pitch, nir_ssa_def *meta_slice_size, nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z, nir_ssa_def *pipe_xor, nir_ssa_def **bit_position) gfx10_nir_meta_addr_from_coord() argument
3179 gfx9_nir_meta_addr_from_coord(nir_builder *b, const struct radeon_info *info, struct gfx9_meta_equation *equation, nir_ssa_def *meta_pitch, nir_ssa_def *meta_height, nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z, nir_ssa_def *sample, nir_ssa_def *pipe_xor, nir_ssa_def **bit_position) gfx9_nir_meta_addr_from_coord() argument
3247 ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info *info, unsigned bpe, struct gfx9_meta_equation *equation, nir_ssa_def *dcc_pitch, nir_ssa_def *dcc_height, nir_ssa_def *dcc_slice_size, nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z, nir_ssa_def *sample, nir_ssa_def *pipe_xor) ac_nir_dcc_addr_from_coord() argument
3267 ac_nir_cmask_addr_from_coord(nir_builder *b, const struct radeon_info *info, struct gfx9_meta_equation *equation, nir_ssa_def *cmask_pitch, nir_ssa_def *cmask_height, nir_ssa_def *cmask_slice_size, nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z, nir_ssa_def *pipe_xor, nir_ssa_def **bit_position) ac_nir_cmask_addr_from_coord() argument
3288 ac_nir_htile_addr_from_coord(nir_builder *b, const struct radeon_info *info, struct gfx9_meta_equation *equation, nir_ssa_def *htile_pitch, nir_ssa_def *htile_slice_size, nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z, nir_ssa_def *pipe_xor) ac_nir_htile_addr_from_coord() argument
[all...] |
| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| H A D | si_shaderlib_nir.c | 173 zero, zero, zero); /* z, sample, pipe_xor */ in si_create_dcc_retile_cs()
181 zero, zero, zero); /* z, sample, pipe_xor */ in si_create_dcc_retile_cs()
201 nir_ssa_def *dcc_pitch, *dcc_height, *clear_value, *pipe_xor; in gfx9_create_clear_dcc_msaa_cs() local
203 unpack_2x16(&b, nir_channel(&b, user_sgprs, 1), &clear_value, &pipe_xor); in gfx9_create_clear_dcc_msaa_cs()
222 zero, pipe_xor); /* sample, pipe_xor */ in gfx9_create_clear_dcc_msaa_cs()
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