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Searched refs:pipe_aligned (Results 1 - 12 of 12) sorted by relevance

/third_party/mesa3d/src/amd/common/
H A Dac_surface_meta_address_test.c60 * bpp, number of fragments, pipe_aligned, rb_aligned */ in gfx9_meta_addr_from_coord()
175 /* equation varies with bpp and pipe_aligned */ in gfx10_dcc_addr_from_coord()
198 unsigned swizzle_mode, bool pipe_aligned, bool rb_aligned, in one_dcc_address_test()
214 in.dccKeyFlags.pipeAligned = din.dccKeyFlags.pipeAligned = pipe_aligned; in one_dcc_address_test()
241 xin.flags.metaPipeUnaligned = !pipe_aligned; in one_dcc_address_test()
371 for (int pipe_aligned = true; pipe_aligned >= (samples > 1 ? true : false); pipe_aligned--) { in run_dcc_address_test()
377 width, height, depth, bpp, samples, rb_aligned, pipe_aligned); in run_dcc_address_test()
380 bpp, swizzle_modes[swizzle_mode], pipe_aligned, in run_dcc_address_test()
195 one_dcc_address_test(const char *name, const char *test, ADDR_HANDLE addrlib, const struct radeon_info *info, unsigned width, unsigned height, unsigned depth, unsigned samples, unsigned bpp, unsigned swizzle_mode, bool pipe_aligned, bool rb_aligned, unsigned mrt_index, unsigned start_x, unsigned start_y, unsigned start_z, unsigned start_sample) one_dcc_address_test() argument
576 one_cmask_address_test(const char *name, const char *test, ADDR_HANDLE addrlib, const struct radeon_info *info, unsigned width, unsigned height, unsigned depth, unsigned bpp, unsigned swizzle_mode, bool pipe_aligned, bool rb_aligned, unsigned mrt_index, unsigned start_x, unsigned start_y, unsigned start_z) one_cmask_address_test() argument
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H A Dac_surface_modifier_test.c71 bool rb_aligned, bool pipe_aligned) in get_addr_from_coord_base()
86 din.dccKeyFlags.pipeAligned = surf->u.gfx9.color.dcc.pipe_aligned; in get_addr_from_coord_base()
101 dcc_input.dccKeyFlags.pipeAligned = pipe_aligned; in get_addr_from_coord_base()
149 surf->u.gfx9.color.dcc.pipe_aligned); in generate_hash()
69 get_addr_from_coord_base(ADDR_HANDLE addrlib, const struct radeon_surf *surf, unsigned w, unsigned h, enum pipe_format format, bool rb_aligned, bool pipe_aligned) get_addr_from_coord_base() argument
H A Dac_surface.c1593 bool pipe_aligned) in is_dcc_supported_by_DCN()
1603 if (info->use_display_dcc_unaligned && (rb_aligned || pipe_aligned)) in is_dcc_supported_by_DCN()
1927 surf->u.gfx9.color.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned; in gfx9_compute_miptree()
2001 assert(surf->u.gfx9.color.dcc.pipe_aligned || surf->u.gfx9.color.dcc.rb_aligned); in gfx9_compute_miptree()
2381 surf->u.gfx9.color.dcc.pipe_aligned) || in gfx9_compute_surface()
2398 surf->u.gfx9.color.dcc.pipe_aligned)); in gfx9_compute_surface()
2409 surf->u.gfx9.color.dcc.pipe_aligned)) { in gfx9_compute_surface()
2774 surf->u.gfx9.color.dcc.pipe_aligned = G_008F24_META_PIPE_ALIGNED(desc[5]); in ac_surface_set_umd_metadata()
2778 if (!surf->u.gfx9.color.dcc.pipe_aligned && !surf->u.gfx9.color.dcc.rb_aligned) in ac_surface_set_umd_metadata()
2787 surf->u.gfx9.color.dcc.pipe_aligned in ac_surface_set_umd_metadata()
1590 is_dcc_supported_by_DCN(const struct radeon_info *info, const struct ac_surf_config *config, const struct radeon_surf *surf, bool rb_aligned, bool pipe_aligned) is_dcc_supported_by_DCN() argument
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H A Dac_surface.h160 uint8_t pipe_aligned : 1; /* optimal for TC */ member
202 * - pipe_aligned
221 * - pipe_aligned
271 /* Displayable DCC. This is always rb_aligned=0 and pipe_aligned=0.
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_sdma_copy_image.c176 image->planes[0].surface.u.gfx9.color.dcc.pipe_aligned << 31); in radv_sdma_v4_v5_copy_image_to_buffer()
H A Dradv_image.c829 .pipe_aligned = 1, in si_set_mutable_tex_desc_fields()
838 state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) | in si_set_mutable_tex_desc_fields()
860 .pipe_aligned = 1, in si_set_mutable_tex_desc_fields()
867 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) | in si_set_mutable_tex_desc_fields()
H A Dradv_device.c6268 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.color.dcc.pipe_aligned); in radv_initialise_color_surface()
6273 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.color.dcc.pipe_aligned); in radv_initialise_color_surface()
6277 .pipe_aligned = 1, in radv_initialise_color_surface()
6286 S_028C74_PIPE_ALIGNED(meta.pipe_aligned); in radv_initialise_color_surface()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_compute_blit.c596 ((struct si_texture*)images[i].resource)->surface.u.gfx9.color.dcc.pipe_aligned); in si_launch_grid_internal_images()
889 ((struct si_texture*)tex)->surface.u.gfx9.color.dcc.pipe_aligned); in si_compute_expand_fmask()
H A Dsi_sdma_copy_image.c215 tiled->surface.u.gfx9.color.dcc.pipe_aligned << 31); in si_sdma_v4_v5_copy_texture()
H A Dsi_descriptors.c355 .pipe_aligned = 1, in si_set_mutable_tex_desc_fields()
361 state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) | in si_set_mutable_tex_desc_fields()
405 .pipe_aligned = 1, in si_set_mutable_tex_desc_fields()
412 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) | in si_set_mutable_tex_desc_fields()
H A Dsi_state.c3083 if (sctx->gfx_level >= GFX9 && !tex->surface.u.gfx9.color.dcc.pipe_aligned) in si_set_framebuffer_state()
3297 S_028EE0_DCC_PIPE_ALIGNED(tex->surface.u.gfx9.color.dcc.pipe_aligned); in si_emit_framebuffer_state()
3329 S_028EE0_DCC_PIPE_ALIGNED(tex->surface.u.gfx9.color.dcc.pipe_aligned); in si_emit_framebuffer_state()
3358 .pipe_aligned = 1, in si_emit_framebuffer_state()
3374 S_028C74_PIPE_ALIGNED(meta.pipe_aligned); in si_emit_framebuffer_state()
H A Dsi_blit.c542 tex->surface.u.gfx9.color.dcc.pipe_aligned); in si_blit_decompress_color()

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