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Searched refs:output_reg (Results 1 - 9 of 9) sorted by relevance

/third_party/mesa3d/src/intel/compiler/
H A Dbrw_vec4_visitor.cpp806 if (output_reg[VARYING_SLOT_POS][0].file == BAD_FILE) in emit_ndc_computation()
810 src_reg pos = src_reg(output_reg[VARYING_SLOT_POS][0]); in emit_ndc_computation()
814 output_reg[BRW_VARYING_SLOT_NDC][0] = ndc; in emit_ndc_computation()
835 output_reg[VARYING_SLOT_CLIP_DIST0][0].file != BAD_FILE || in emit_psiz_and_flags()
844 src_reg psiz = src_reg(output_reg[VARYING_SLOT_PSIZ][0]); in emit_psiz_and_flags()
851 if (output_reg[VARYING_SLOT_CLIP_DIST0][0].file != BAD_FILE) { in emit_psiz_and_flags()
855 emit(CMP(dst_null_f(), src_reg(output_reg[VARYING_SLOT_CLIP_DIST0][0]), brw_imm_f(0.0f), BRW_CONDITIONAL_L)); in emit_psiz_and_flags()
860 if (output_reg[VARYING_SLOT_CLIP_DIST1][0].file != BAD_FILE) { in emit_psiz_and_flags()
862 emit(CMP(dst_null_f(), src_reg(output_reg[VARYING_SLOT_CLIP_DIST1][0]), brw_imm_f(0.0f), BRW_CONDITIONAL_L)); in emit_psiz_and_flags()
878 output_reg[BRW_VARYING_SLOT_ND in emit_psiz_and_flags()
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H A Dbrw_vec4_vs_visitor.cpp61 output_reg[varying][0].type = reg.type; in emit_urb_slot()
H A Dgfx6_gs_visitor.cpp414 reg.type = output_reg[varying][0].type; in emit_thread_end()
651 data.type = output_reg[varying][0].type; in xfb_program()
H A Dbrw_vec4.h121 dst_reg output_reg[VARYING_SLOT_TESS_MAX][4]; member in brw::vec4_visitor
H A Dbrw_vec4_nir.cpp424 output_reg[varying][c] = dst_reg(src); in nir_emit_intrinsic()
/third_party/mesa3d/src/gallium/drivers/r300/compiler/
H A Dradeon_program_tex.c164 struct rc_dst_register output_reg = inst->U.I.DstReg; in radeonTransformTEX() local
246 inst_cmp->U.I.DstReg = output_reg; in radeonTransformTEX()
/third_party/node/deps/v8/src/compiler/backend/x64/
H A Dcode-generator-x64.cc2015 Register output_reg = i.OutputRegister(0); in AssembleArchInstruction() local
2018 __ Cvttss2siq(output_reg, i.InputDoubleRegister(0)); in AssembleArchInstruction()
2020 __ Cvttss2siq(output_reg, i.InputOperand(0)); in AssembleArchInstruction()
2030 __ Cvttss2siq(output_reg, i.InputDoubleRegister(0)); in AssembleArchInstruction()
2035 __ Cvttss2siq(output_reg, rounded); in AssembleArchInstruction()
2038 __ Cvtqsi2ss(converted_back, output_reg); in AssembleArchInstruction()
2064 __ cmpq(output_reg, Immediate(1)); in AssembleArchInstruction()
2075 Register output_reg = i.OutputRegister(0); in AssembleArchInstruction() local
2078 __ Cvttsd2siq(output_reg, i.InputDoubleRegister(0)); in AssembleArchInstruction()
2080 __ Cvttsd2siq(output_reg, in AssembleArchInstruction()
[all...]
/third_party/python/Lib/test/
H A Dtest_tarfile.py1732 output_reg = tar.getmember("my_regular_file")
1737 self.assertEqual(output_reg.devmajor, 0)
1738 self.assertEqual(output_reg.devminor, 0)
1744 buf_reg = buf[output_reg.offset:output_reg.offset_data]
/third_party/mesa3d/src/gallium/drivers/svga/
H A Dsvga_tgsi_vgpu10.c12309 unsigned output_reg = emit->fs.color_out_index[i]; in emit_broadcast_color_instructions() local
12311 make_dst_output_reg(output_reg); in emit_broadcast_color_instructions()
12316 emit->info.output_semantic_name[output_reg] = TGSI_SEMANTIC_COLOR; in emit_broadcast_color_instructions()

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