Searched refs:opc1 (Results 1 - 4 of 4) sorted by relevance
| /third_party/mesa3d/src/nouveau/codegen/ |
| H A D | nv50_ir_emit_gk110.cpp | 46 void emitForm_21(const Instruction *, uint32_t opc2, uint32_t opc1);
424 uint32_t opc1) in emitForm_21()
434 code[1] = opc1 << 20; in emitForm_21()
1855 uint64_t opc1, opc2; in emitSUCalc() local
1864 case OP_SUCLAMP: opc1 = 0xb00; opc2 = 0x580; break; in emitSUCalc()
1865 case OP_SUBFM: opc1 = 0xb68; opc2 = 0x1e8; break; in emitSUCalc()
1866 case OP_SUEAU: opc1 = 0xb6c; opc2 = 0x1ec; break; in emitSUCalc()
1871 emitForm_21(i, opc2, opc1); in emitSUCalc()
423 emitForm_21(const Instruction *i, uint32_t opc2, uint32_t opc1) emitForm_21() argument
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| /third_party/node/deps/v8/src/execution/arm/ |
| H A D | simulator-arm.cc | 3543 int opc1 = instr->Bits(23, 21); in DecodeTypeCP15() local
3545 if ((opc1 == 0) && (crn == 7)) { in DecodeTypeCP15()
4399 int opc1 = instr->Bits(17, 16); in DecodeAdvancedSIMDTwoOrThreeRegisters() local
4403 if (opc1 == 0 && (opc2 >> 2) == 0) { in DecodeAdvancedSIMDTwoOrThreeRegisters()
4485 } else if (opc1 == 0 && (opc2 == 0b0100 || opc2 == 0b0101)) { in DecodeAdvancedSIMDTwoOrThreeRegisters()
4507 } else if (opc1 == 0 && (opc2 == 0b1100 || opc2 == 0b1101)) { in DecodeAdvancedSIMDTwoOrThreeRegisters()
4532 } else if (size == 0 && opc1 == 0b10 && opc2 == 0) { in DecodeAdvancedSIMDTwoOrThreeRegisters()
4552 } else if (opc1 == 0 && opc2 == 0b1010) { in DecodeAdvancedSIMDTwoOrThreeRegisters()
4563 } else if (opc1 == 0 && opc2 == 0b1011) { in DecodeAdvancedSIMDTwoOrThreeRegisters()
4571 } else if (opc1 in DecodeAdvancedSIMDTwoOrThreeRegisters()
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| /third_party/backends/backend/ |
| H A D | umax1220u-common.c | 581 unsigned char opc1[16] = { in cwritev_opc1_lamp_ctrl() local
588 opc1[14] = (state == UMAX_LAMP_OFF) ? 0x90 : 0xf0; in cwritev_opc1_lamp_ctrl()
589 return cwritev (scan, CMD_2, 16, opc1, NULL); in cwritev_opc1_lamp_ctrl()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 5844 unsigned opc1 = fieldFromInstruction(Val, 4, 4); in DecoderForMRRC2AndMCRR2() local
5862 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] in DecoderForMRRC2AndMCRR2()
5863 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] in DecoderForMRRC2AndMCRR2()
5872 Inst.addOperand(MCOperand::createImm(opc1)); in DecoderForMRRC2AndMCRR2()
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