| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| H A D | si_sdma_copy_image.c | 229 uint64_t dst_address = sdst->buffer.gpu_address + sdst->surface.u.legacy.level[0].offset_256B * 256; in cik_sdma_copy_texture()
230 uint64_t src_address = ssrc->buffer.gpu_address + ssrc->surface.u.legacy.level[0].offset_256B * 256; in cik_sdma_copy_texture()
366 linear->surface.u.legacy.level[0].offset_256B * 256; in cik_sdma_copy_texture()
369 linear->surface.u.legacy.level[0].offset_256B * 256 + in cik_sdma_copy_texture()
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| H A D | radeon_vce_50.c | 121 (uint64_t)enc->luma->u.legacy.level[0].offset_256B * 256); // inputPictureLumaAddressHi/Lo in encode()
123 (uint64_t)enc->chroma->u.legacy.level[0].offset_256B * 256); // inputPictureChromaAddressHi/Lo in encode()
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| H A D | radeon_vce_40_2_2.c | 311 (uint64_t)enc->luma->u.legacy.level[0].offset_256B * 256); // inputPictureLumaAddressHi/Lo in encode()
313 (uint64_t)enc->chroma->u.legacy.level[0].offset_256B * 256); // inputPictureChromaAddressHi/Lo in encode()
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| H A D | si_texture.c | 161 return (uint64_t)tex->surface.u.legacy.level[level].offset_256B * 256; in si_texture_get_offset()
165 return (uint64_t)tex->surface.u.legacy.level[level].offset_256B * 256 + in si_texture_get_offset()
875 i, (uint64_t)tex->surface.u.legacy.level[i].offset_256B * 256, in si_print_texture_info()
889 i, (uint64_t)tex->surface.u.legacy.zs.stencil_level[i].offset_256B * 256, in si_print_texture_info()
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| H A D | radeon_uvd_enc_1_1.c | 901 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, (uint64_t)enc->luma->u.legacy.level[0].offset_256B * 256); in radeon_uvd_enc_encode_params_hevc()
902 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, (uint64_t)enc->chroma->u.legacy.level[0].offset_256B * 256); in radeon_uvd_enc_encode_params_hevc()
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| H A D | radeon_vce_52.c | 266 (uint64_t)enc->luma->u.legacy.level[0].offset_256B * 256); // inputPictureLumaAddressHi/Lo in encode()
268 (uint64_t)enc->chroma->u.legacy.level[0].offset_256B * 256); // inputPictureChromaAddressHi/Lo in encode()
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| H A D | radeon_uvd.c | 1382 return (uint64_t)surface->u.legacy.level[0].offset_256B * 256 + in texture_offset()
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| H A D | si_state.c | 2764 (tex->buffer.gpu_address >> 8) + tex->surface.u.legacy.level[level].offset_256B; in si_init_depth_surface()
2766 (tex->buffer.gpu_address >> 8) + tex->surface.u.legacy.zs.stencil_level[level].offset_256B; in si_init_depth_surface()
3402 cb_color_base += level_info->offset_256B; in si_emit_framebuffer_state()
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| H A D | si_descriptors.c | 309 va += (uint64_t)base_level_info->offset_256B * 256; in si_set_mutable_tex_desc_fields()
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| /third_party/mesa3d/src/gallium/winsys/radeon/drm/ |
| H A D | radeon_drm_surface.c | 70 level_drm->offset = (uint64_t)level_ws->offset_256B * 256; in surf_level_winsys_to_drm()
82 level_ws->offset_256B = level_drm->offset / 256; in surf_level_drm_to_winsys()
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| /third_party/mesa3d/src/gallium/drivers/r600/ |
| H A D | r600_state.c | 763 view->tex_resource_words[2] = tmp->surface.u.legacy.level[offset_level].offset_256B; in r600_create_sampler_view_custom()
765 view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level].offset_256B; in r600_create_sampler_view_custom()
767 view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level + 1].offset_256B; in r600_create_sampler_view_custom()
832 offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256; in r600_init_color_surface()
1049 offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256; in r600_init_depth_surface()
2895 base = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256; in r600_dma_copy_tile()
2896 addr = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256; in r600_dma_copy_tile()
2914 base = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256; in r600_dma_copy_tile()
2915 addr = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256; in r600_dma_copy_tile()
3018 src_offset= (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 25 in r600_dma_copy()
[all...] |
| H A D | r600_texture.c | 186 return (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256; in r600_texture_get_offset()
190 return (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256 + in r600_texture_get_offset()
265 surface->u.legacy.level[i].offset_256B += offset / 256; in r600_init_surface()
458 offset = (uint64_t)rtex->surface.u.legacy.level[0].offset_256B * 256; in r600_texture_get_info()
864 i, (uint64_t)rtex->surface.u.legacy.level[i].offset_256B * 256, in r600_print_texture_info()
882 i, (uint64_t)rtex->surface.u.legacy.zs.stencil_level[i].offset_256B * 256, in r600_print_texture_info()
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| H A D | radeon_video.c | 183 surfaces[i]->u.legacy.level[j].offset_256B += off / 256; in rvid_join_surfaces()
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| H A D | evergreen_state.c | 855 tex_resource_words[2] = ((uint64_t)surflevel[base_level].offset_256B * 256 + va) >> 8; in evergreen_fill_tex_resource_words()
869 tex_resource_words[3] = ((uint64_t)surflevel[1].offset_256B * 256 + va) >> 8; in evergreen_fill_tex_resource_words()
871 tex_resource_words[3] = ((uint64_t)surflevel[base_level].offset_256B * 256 + va) >> 8; in evergreen_fill_tex_resource_words()
1132 color->offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256; in evergreen_set_color_surface_common()
1369 offset += (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256; in evergreen_init_depth_surface()
1419 stencil_offset = (uint64_t)rtex->surface.u.legacy.zs.stencil_level[level].offset_256B * 256; in evergreen_init_depth_surface()
3816 base = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256; in evergreen_dma_copy_tile()
3817 addr = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256; in evergreen_dma_copy_tile()
3841 base = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256; in evergreen_dma_copy_tile()
3842 addr = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 25 in evergreen_dma_copy_tile()
[all...] |
| H A D | radeon_uvd.c | 1173 return (uint64_t)surface->u.legacy.level[0].offset_256B * 256 + in texture_offset()
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| /third_party/mesa3d/src/amd/common/ |
| H A D | ac_surface.h | 93 uint32_t offset_256B; /* divided by 256, the hw can only do 40-bit addresses */ member
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| H A D | ac_surface.c | 695 surf_level->offset_256B = align64(surf->surf_size, AddrSurfInfoOut->baseAlign) / 256; in gfx6_compute_level()
734 surf->surf_size = (uint64_t)surf_level->offset_256B * 256 + AddrSurfInfoOut->surfSize; in gfx6_compute_level()
2725 offset = (uint64_t)surf->u.legacy.level[0].offset_256B * 256; in ac_surface_set_umd_metadata()
2857 metadata[10 + i] = surf->u.legacy.level[i].offset_256B; in ac_surface_get_umd_metadata()
2934 surf->u.legacy.level[i].offset_256B += offset / 256; in ac_surface_override_offset_stride()
2975 return (uint64_t)surf->u.legacy.level[0].offset_256B * 256 + in ac_surface_get_plane_offset()
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| /third_party/mesa3d/src/amd/vulkan/ |
| H A D | radv_image.c | 785 va += (uint64_t)base_level_info->offset_256B * 256; in si_set_mutable_tex_desc_fields()
2454 pLayout->offset = (uint64_t)surface->u.legacy.level[level].offset_256B * 256 + in radv_GetImageSubresourceLayout()
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| H A D | radv_device.c | 4848 offset = (uint64_t)surface->u.legacy.level[level].offset_256B * 256 + in radv_sparse_image_bind_memory()
6296 cb->cb_color_base += level_info->offset_256B; in radv_initialise_color_surface()
6662 z_offs += (uint64_t)surf->u.legacy.level[level].offset_256B * 256; in radv_initialise_ds_surface()
6663 s_offs += (uint64_t)surf->u.legacy.zs.stencil_level[level].offset_256B * 256; in radv_initialise_ds_surface()
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| H A D | radv_formats.c | 1977 .offset_256B * 256; in radv_GetImageSparseMemoryRequirements2()
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