| /third_party/lame/mpglib/ |
| H A D | layer2.c | 86 table = muls[k]; in hip_init_tables_layer2()
245 cm = muls[k][x1]; in II_step_two()
256 r0 = muls[k0][x1]; in II_step_two()
257 r1 = muls[k1][x1]; in II_step_two()
258 r2 = muls[k2][x1]; in II_step_two()
288 cm = muls[k][x1]; in II_step_two()
307 r0 = muls[k0][x1]; in II_step_two()
308 r1 = muls[k1][x1]; in II_step_two()
309 r2 = muls[k2][x1]; in II_step_two()
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| H A D | layer1.c | 131 r0 = (((-1) << n0) + v + 1) * muls[n0 + 1][i0]; in I_step_two()
138 r1 = (((-1) << n1) + v + 1) * muls[n1 + 1][i1]; in I_step_two()
156 r0 = w * muls[n + 1][i0]; in I_step_two()
157 r1 = w * muls[n + 1][i1]; in I_step_two()
178 r0 = (((-1) << n) + v + 1) * muls[n + 1][j]; in I_step_two()
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| H A D | common.h | 32 extern real muls[27][64];
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| H A D | common.c | 75 real muls[27][64]; variable
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| /third_party/ffmpeg/libavcodec/ppc/ |
| H A D | lossless_audiodsp_altivec.c | 52 register vec_s16 muls = { mul, mul, mul, mul, mul, mul, mul, mul }; in scalarproduct_and_madd_int16_altivec() local
70 pv1[0] = vec_mladd(t0, muls, i0); in scalarproduct_and_madd_int16_altivec()
71 pv1[1] = vec_mladd(t1, muls, i1); in scalarproduct_and_madd_int16_altivec()
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| /third_party/ffmpeg/libavcodec/arm/ |
| H A D | simple_idct_arm.S | 109 teq r2, #0 @ if null avoid muls
138 teq r3, #0 @ if null avoid muls
148 teq r4, #0 @ if null avoid muls
198 teq r11, #0 @ if null avoid muls
209 teq r9, #0 @ if null avoid muls
320 teq r2, #0 @ if 0, then avoid muls
341 teq r3, #0 @ if 0 then avoid muls
351 teq r4, #0 @ if 0 then avoid muls
393 teq r11, #0 @ if null avoid muls
404 teq r9, #0 @ if null avoid muls
[all...] |
| H A D | h264cmc_neon.S | 48 A muls r7, r4, r5
223 A muls r7, r4, r5
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| /third_party/vixl/test/aarch32/ |
| H A D | test-assembler-cond-rdlow-rnlow-rmlow-t32.cc | 51 #define FOREACH_INSTRUCTION(M) M(muls)
162 #include "aarch32/traces/assembler-cond-rdlow-rnlow-rmlow-muls-t32.h"
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| H A D | test-assembler-cond-rd-rn-rm-a32.cc | 53 M(muls) \
457 #include "aarch32/traces/assembler-cond-rd-rn-rm-muls-a32.h"
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| /third_party/mesa3d/src/nouveau/codegen/ |
| H A D | nv50_ir_lowering_nv50.cpp | 1745 Value *muls[2]; in processSurfaceCoords() local
1746 bld.mkSplit(muls, 2, mul->getDef(0)); in processSurfaceCoords()
1748 coords[1] = bld.mkOp2v(OP_ADD, TYPE_U16, bld.getSSA(2), coords[1], muls[0]); in processSurfaceCoords()
1750 coords[1] = muls[0]; in processSurfaceCoords()
1816 Value *muls[2]; in processSurfaceCoords() local
1817 bld.mkSplit(muls, 2, mul->getDef(0)); in processSurfaceCoords()
1821 muls[0], in processSurfaceCoords()
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| H A D | nv50_ir_peephole.cpp | 1493 int muls; in opnd() local
1499 muls = 1; in opnd()
1501 muls = 0; in opnd()
1510 i->setSrc(0, si->getSrc(!muls)); in opnd()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/DartARM32/ |
| H A D | assembler_arm.h | 506 void muls(Register rd, Register rn, Register rm, Condition cond = AL);
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| H A D | assembler_arm.cc | 367 void Assembler::muls(Register rd, Register rn, Register rm, Condition cond) {
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| /third_party/vixl/src/aarch32/ |
| H A D | assembler-aarch32.h | 2693 void muls(Condition cond, Register rd, Register rn, Register rm);
2694 void muls(Register rd, Register rn, Register rm) { muls(al, rd, rn, rm); } in muls() function in vixl::aarch32::Assembler
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| H A D | disasm-aarch32.h | 952 void muls(Condition cond, Register rd, Register rn, Register rm);
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| H A D | assembler-aarch32.cc | 7488 void Assembler::muls(Condition cond, Register rd, Register rn, Register rm) { in muls() function in vixl::aarch32::Assembler
7507 Delegate(kMuls, &Assembler::muls, cond, rd, rn, rm); in muls()
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| H A D | disasm-aarch32.cc | 1970 void Disassembler::muls(Condition cond, Register rd, Register rn, Register rm) { in muls() function in vixl::aarch32::Disassembler
7616 muls(Condition::None(), in DecodeT32()
[all...] |
| H A D | macro-assembler-aarch32.h | 3073 muls(cond, rd, rn, rm); in MacroAssembler()
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