Home
last modified time | relevance | path

Searched refs:midgard_reg_mode_8 (Results 1 - 5 of 5) sorted by relevance

/third_party/mesa3d/src/panfrost/midgard/
H A Ddisassemble.c136 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
141 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
146 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
151 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
155 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
356 case midgard_reg_mode_8: in bits_for_mode()
426 bool is_vec16 = reg_mode == midgard_reg_mode_8; in print_vec_selectors()
512 if (mode == midgard_reg_mode_8 || mode == midgard_reg_mode_16) in print_vec_swizzle()
819 bool shrinkable = (mode != midgard_reg_mode_8); in print_vector_field()
H A Dmidgard_print_constant.c146 case midgard_reg_mode_8: in mir_print_constant_component()
H A Dmidgard_ops.c201 #define M8 midgard_reg_mode_8
H A Dmidgard.h253 midgard_reg_mode_8 = 0, enumerator
H A Dmidgard_emit.c316 } else if (reg_mode == midgard_reg_mode_8) { in mir_pack_swizzle()

Completed in 8 milliseconds