Searched refs:midgard_reg_mode (Results 1 - 8 of 8) sorted by relevance
| /third_party/mesa3d/src/panfrost/midgard/ |
| H A D | disassemble.c | 129 midgard_reg_mode reg_mode) in validate_expand_mode()
353 bits_for_mode(midgard_reg_mode mode) in bits_for_mode()
371 bits_for_mode_halved(midgard_reg_mode mode, bool half) in bits_for_mode_halved()
383 midgard_reg_mode reg_mode, in print_vec_selectors_64()
418 midgard_reg_mode reg_mode, in print_vec_selectors()
448 midgard_reg_mode mode, in print_vec_swizzle()
645 midgard_reg_mode mode, unsigned reg, in print_vector_src()
796 midgard_reg_mode mode = alu_field->reg_mode; in print_vector_field()
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| H A D | midgard_print_constant.c | 34 midgard_reg_mode reg_mode, bool half, in mir_print_constant_component()
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| H A D | midgard.h | 257 } midgard_reg_mode; typedef
278 /* The expand options depend on both midgard_int_mod and midgard_reg_mode. For
315 midgard_reg_mode reg_mode : 2;
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| H A D | midgard_print.c | 127 midgard_reg_mode reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins)); in mir_print_embedded_constant()
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| H A D | helpers.h | 274 /* Lower 2-bits are a midgard_reg_mode */
435 unsigned c, midgard_reg_mode reg_mode, bool half,
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| H A D | compiler.h | 508 midgard_reg_mode reg_mode_for_bitsize(unsigned bitsize);
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| H A D | midgard_emit.c | 234 midgard_reg_mode reg_mode = reg_mode_for_bitsize(base_size); in mir_pack_swizzle()
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| H A D | midgard_compile.c | 2685 midgard_reg_mode
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