| /third_party/mesa3d/src/freedreno/fdl/ |
| H A D | fd6_layout.c | 260 uint32_t meta_pitch = fdl_ubwc_pitch(layout, level); in fdl6_layout() local
265 align(meta_pitch * meta_height, UBWC_PLANE_SIZE_ALIGNMENT); in fdl6_layout()
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| /third_party/mesa3d/src/amd/common/ |
| H A D | ac_surface_meta_address_test.c | 65 unsigned meta_pitch, unsigned meta_height, in gfx9_meta_addr_from_coord()
78 unsigned pitchInBlock = meta_pitch >> meta_block_width_log2; in gfx9_meta_addr_from_coord()
126 unsigned meta_pitch, unsigned meta_slice_size, in gfx10_meta_addr_from_coord()
160 unsigned pb = meta_pitch >> meta_block_width_log2; in gfx10_meta_addr_from_coord()
57 gfx9_meta_addr_from_coord(const struct radeon_info *info, const struct gfx9_addr_meta_equation *eq, unsigned meta_block_width, unsigned meta_block_height, unsigned meta_block_depth, unsigned meta_pitch, unsigned meta_height, unsigned x, unsigned y, unsigned z, unsigned sample, unsigned pipe_xor, unsigned *bit_position) gfx9_meta_addr_from_coord() argument
120 gfx10_meta_addr_from_coord(const struct radeon_info *info, const uint16_t *equation, unsigned meta_block_width, unsigned meta_block_height, unsigned blkSizeLog2, unsigned meta_pitch, unsigned meta_slice_size, unsigned x, unsigned y, unsigned z, unsigned pipe_xor, unsigned *bit_position) gfx10_meta_addr_from_coord() argument
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| H A D | ac_surface.h | 371 uint32_t meta_pitch; member
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| H A D | ac_surface.c | 835 surf->meta_pitch = AddrHtileOut->pitch; in gfx6_compute_level()
1831 surf->meta_pitch = hout.pitch; in gfx9_compute_miptree()
3126 nir_ssa_def *meta_pitch, nir_ssa_def *meta_slice_size, in gfx10_nir_meta_addr_from_coord()
3165 nir_ssa_def *pb = nir_ushr_imm(b, meta_pitch, meta_block_width_log2); in gfx10_nir_meta_addr_from_coord()
3181 nir_ssa_def *meta_pitch, nir_ssa_def *meta_height, in gfx9_nir_meta_addr_from_coord()
3197 nir_ssa_def *pitchInBlock = nir_ushr_imm(b, meta_pitch, meta_block_width_log2); in gfx9_nir_meta_addr_from_coord()
3123 gfx10_nir_meta_addr_from_coord(nir_builder *b, const struct radeon_info *info, struct gfx9_meta_equation *equation, int blkSizeBias, unsigned blkStart, nir_ssa_def *meta_pitch, nir_ssa_def *meta_slice_size, nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z, nir_ssa_def *pipe_xor, nir_ssa_def **bit_position) gfx10_nir_meta_addr_from_coord() argument
3179 gfx9_nir_meta_addr_from_coord(nir_builder *b, const struct radeon_info *info, struct gfx9_meta_equation *equation, nir_ssa_def *meta_pitch, nir_ssa_def *meta_height, nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z, nir_ssa_def *sample, nir_ssa_def *pipe_xor, nir_ssa_def **bit_position) gfx9_nir_meta_addr_from_coord() argument
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| /third_party/mesa3d/src/amd/vulkan/ |
| H A D | radv_meta_copy_vrs_htile.c | 284 dst_image->planes[0].surface.meta_pitch, dst_image->planes[0].surface.meta_slice_size, in radv_copy_vrs_htile()
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