| /third_party/vixl/test/aarch64/ |
| H A D | test-abi.cc | 78 #define CHECK_NEXT_PARAMETER_MEM(type, mem_op, size) \ in TEST()
80 expected = GenericOperand(mem_op, size); \ in TEST()
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| /third_party/mesa3d/src/gallium/drivers/r600/sb/ |
| H A D | sb_bc_decoder.cpp | 414 unsigned mem_op = (dw0 >> 8) & 0x7; in decode_fetch() local
416 if (mem_op == 0 || mem_op == 2) { in decode_fetch()
417 fetch_opcode = mem_op == 0 ? FETCH_OP_READ_SCRATCH : FETCH_OP_READ_MEM; in decode_fetch()
418 } else if (mem_op == 4) { in decode_fetch()
424 } else if (mem_op == 5) in decode_fetch()
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| H A D | sb_bc_builder.cpp | 569 unsigned mem_op = 4; in build_fetch_gds() local
573 mem_op = 5; in build_fetch_gds()
579 .MEM_OP(mem_op) in build_fetch_gds()
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| /third_party/libbpf/include/uapi/linux/ |
| H A D | perf_event.h | 1270 __u64 mem_op:5, /* type of opcode */ member
1297 mem_op:5; /* type of opcode */ member
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| /third_party/vixl/src/aarch64/ |
| H A D | operands-aarch64.cc | 439 GenericOperand::GenericOperand(const MemOperand& mem_op, size_t mem_op_size) in GenericOperand() argument
440 : cpu_register_(NoReg), mem_op_(mem_op), mem_op_size_(mem_op_size) { in GenericOperand()
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| H A D | macro-assembler-aarch64.cc | 1865 const MemOperand& mem_op) { in Emit()
1867 VIXL_ASSERT(mem_op.GetAddrMode() == Offset); in Emit()
1868 Register base = mem_op.GetBaseRegister(); in Emit()
1869 if (mem_op.IsImmediateOffset()) { in Emit()
1870 Add(dst, base, mem_op.GetOffset()); in Emit()
1872 VIXL_ASSERT(mem_op.IsRegisterOffset()); in Emit()
1873 Register reg_offset = mem_op.GetRegisterOffset(); in Emit()
1874 Shift shift = mem_op.GetShift(); in Emit()
1875 Extend extend = mem_op.GetExtend(); in Emit()
1878 Add(dst, base, Operand(reg_offset, extend, mem_op in Emit()
1864 ComputeAddress(const Register& dst, const MemOperand& mem_op) Emit() argument
[all...] |
| H A D | operands-aarch64.h | 941 GenericOperand(const MemOperand& mem_op,
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| H A D | simulator-aarch64.cc | 1133 uint64_t Simulator::ComputeMemOperandAddress(const MemOperand& mem_op) const { in Simulator()
1134 VIXL_ASSERT(mem_op.IsValid()); in Simulator()
1135 int64_t base = ReadRegister<int64_t>(mem_op.GetBaseRegister()); in Simulator()
1136 if (mem_op.IsImmediateOffset()) { in Simulator()
1137 return base + mem_op.GetOffset(); in Simulator()
1139 VIXL_ASSERT(mem_op.GetRegisterOffset().IsValid()); in Simulator()
1140 int64_t offset = ReadRegister<int64_t>(mem_op.GetRegisterOffset()); in Simulator()
1141 unsigned shift_amount = mem_op.GetShiftAmount(); in Simulator()
1142 if (mem_op.GetShift() != NO_SHIFT) { in Simulator()
1143 offset = ShiftOperand(kXRegSize, offset, mem_op in Simulator()
[all...] |
| H A D | assembler-sve-aarch64.cc | 3827 Instr mem_op = SVEMemOperandHelper(msize_in_bytes_log2, 1, addr); in SVELdSt1Helper() local
3830 Emit(op | mem_op | dtype | Rt(zt) | PgLow8(pg)); in SVELdSt1Helper()
3843 Instr mem_op = SVEMemOperandHelper(msize_in_bytes_log2, num_regs, addr); in SVELdSt234Helper() local
3844 Emit(op | mem_op | msz | num | Rt(zt1) | PgLow8(pg)); in SVELdSt234Helper()
4034 Instr mem_op = SVEMemOperandHelper(msize_in_bytes_log2, 1, addr, is_load); in SVEScatterGatherHelper() local
4038 Emit(op | mem_op | msz | u | ff | Rt(zt) | PgLow8(pg)); in SVEScatterGatherHelper()
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| H A D | simulator-aarch64.h | 2090 uint64_t ComputeMemOperandAddress(const MemOperand& mem_op) const;
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| H A D | macro-assembler-aarch64.h | 871 void ComputeAddress(const Register& dst, const MemOperand& mem_op);
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| /third_party/node/deps/v8/src/wasm/baseline/arm/ |
| H A D | liftoff-assembler-arm.h | 4335 MemOperand mem_op = liftoff::GetStackSlot(slot.src_offset_);
4338 asm_, &temps, mem_op.rn(), no_reg, mem_op.offset());
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| /third_party/mesa3d/src/gallium/drivers/svga/ |
| H A D | svga_tgsi_vgpu10.c | 10030 memory_op mem_op, in emit_memory_register()
10042 switch (mem_op) { in emit_memory_register()
10029 emit_memory_register(struct svga_shader_emitter_v10 *emit, memory_op mem_op, const struct tgsi_full_instruction *inst, unsigned regIndex, unsigned writemask) emit_memory_register() argument
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