/third_party/mesa3d/src/intel/compiler/ |
H A D | brw_fs_bank_conflicts.cpp | 367 max_reg(n), 378 max_reg(p.max_reg), 380 atoms(new unsigned[p.max_reg + num_terminator_atoms]) 385 sizeof(unsigned) * (p.max_reg + num_terminator_atoms)); 397 SWAP(max_reg, p.max_reg); 416 for (unsigned reg1 = reg + 1; reg1 <= max_reg; reg1++) { 463 return atoms[max_reg]; 473 unsigned max_reg; [all...] |
/third_party/mesa3d/src/freedreno/ir3/ |
H A D | ir3_shader.c | 87 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3); in fixup_regfootprint() 90 v->info.max_reg = MAX2(v->info.max_reg, regid >> 2); in fixup_regfootprint() 104 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3); in fixup_regfootprint() 107 v->info.max_reg = MAX2(v->info.max_reg, regid >> 2); in fixup_regfootprint() 118 v->info.max_reg = MAX2(v->info.max_reg, regi in fixup_regfootprint() [all...] |
H A D | ir3.c | 123 info->max_reg = MAX2(info->max_reg, max >> 3); in collect_reg_info() 128 info->max_reg = MAX2(info->max_reg, max >> 2); in collect_reg_info() 274 info->max_reg = -1; in ir3_collect_info() 395 info->max_reg + 1 + in ir3_collect_info()
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H A D | ir3_shader.h | 1149 return (2 * (v->info.max_reg + 1)) + (v->info.max_half_reg + 1);
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H A D | ir3.h | 62 /* NOTE: max_reg, etc, does not include registers not touched 66 int8_t max_reg; /* highest GPR # used by shader */ member
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/third_party/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
H A D | fd2_program.c | 253 fs_gprs = (fpi->max_reg < 0) ? 0x80 : fpi->max_reg; in fd2_program_emit() 257 vs_gprs = (vpi->max_reg < 0) ? 0x80 : vpi->max_reg; in fd2_program_emit()
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H A D | ir2_ra.c | 171 /* update max_reg value */ in ra_reg() 172 ctx->info->max_reg = MAX2(ctx->info->max_reg, (int)idx); in ra_reg()
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H A D | ir2.h | 57 int8_t max_reg; member
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H A D | ir2.c | 453 ctx.info->max_reg = -1; in ir2_compile()
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/third_party/libunwind/libunwind/src/ia64/ |
H A D | Gscript.c | 372 int r, i, j, max, max_reg, max_when, num_regs = 0; in sort_regs() local 391 max_reg = regorder[max]; in sort_regs() 392 max_when = sr->curr.reg[max_reg].when; in sort_regs() 398 max_reg = regorder[j]; in sort_regs() 399 max_when = sr->curr.reg[max_reg].when; in sort_regs() 404 regorder[i] = max_reg; in sort_regs()
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/third_party/mesa3d/src/gallium/drivers/freedreno/a5xx/ |
H A D | fd5_compute.c | 61 A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(i->max_reg + 1) | in cs_program_emit()
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H A D | fd5_program.c | 383 A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) | in fd5_program_emit() 545 A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) | in fd5_program_emit()
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/third_party/mesa3d/src/gallium/drivers/freedreno/a3xx/ |
H A D | fd3_program.c | 238 A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi->max_reg + 1) | in fd3_program_emit() 309 A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi->max_reg + 1) | in fd3_program_emit()
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/third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/ |
H A D | fd6_compute.c | 67 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(i->max_reg + 1) |
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H A D | fd6_program.c | 563 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) | 698 A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(hs->info.max_reg + 1) | 709 A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(ds->info.max_reg + 1) | 864 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) | 963 A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs->info.max_reg + 1) |
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/third_party/mesa3d/src/gallium/drivers/freedreno/a4xx/ |
H A D | fd4_compute.c | 62 A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(i->max_reg + 1)); in cs_program_emit()
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H A D | fd4_program.c | 303 A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) | in fd4_program_emit() 383 A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) | in fd4_program_emit()
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/third_party/mesa3d/src/freedreno/computerator/ |
H A D | a4xx.c | 114 A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(i->max_reg + 1)); in cs_program_emit()
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H A D | a6xx.c | 153 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(i->max_reg + 1) | in cs_program_emit()
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/third_party/mesa3d/src/asahi/compiler/ |
H A D | agx_compile.c | 1321 unsigned nr_ins = 0, max_reg = 0; in agx_print_stats() local 1330 max_reg = MAX2(max_reg, in agx_print_stats() 1343 nr_ins, size, max_reg, nr_threads, ctx->loop_count, in agx_print_stats()
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/third_party/mesa3d/src/gallium/drivers/freedreno/ir3/ |
H A D | ir3_gallium.c | 93 v->info.max_half_reg + 1, v->info.max_reg + 1, v->constlen, in dump_shader_info()
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/third_party/mesa3d/src/freedreno/vulkan/ |
H A D | tu_pipeline.c | 487 .fullregfootprint = xs->info.max_reg + 1, in tu6_emit_xs() 495 .fullregfootprint = xs->info.max_reg + 1, in tu6_emit_xs() 502 .fullregfootprint = xs->info.max_reg + 1, in tu6_emit_xs() 509 .fullregfootprint = xs->info.max_reg + 1, in tu6_emit_xs() 516 .fullregfootprint = xs->info.max_reg + 1, in tu6_emit_xs() 530 .fullregfootprint = xs->info.max_reg + 1, in tu6_emit_xs() 4399 stat->value.u64 = exe->stats.max_reg + 1; in tu_GetPipelineExecutableStatisticsKHR()
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/third_party/node/deps/v8/src/compiler/backend/ |
H A D | mid-tier-register-allocator.cc | 1305 RegisterIndex GetFirstCleared(int max_reg) const { in GetFirstCleared() 1307 if (reg_index < max_reg) { in GetFirstCleared()
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