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Help
Searched
refs:max_dw
(Results
1 - 18
of
18
) sorted by relevance
/third_party/mesa3d/src/amd/vulkan/
H
A
D
radv_cs.h
37
if (cs->
max_dw
- cs->cdw < needed)
in radeon_check_space()
46
assert(cs->cdw + 2 + num <= cs->
max_dw
);
in radeon_set_config_reg_seq()
63
assert(cs->cdw + 2 + num <= cs->
max_dw
);
in radeon_set_context_reg_seq()
80
assert(cs->cdw + 3 <= cs->
max_dw
);
in radeon_set_context_reg_idx()
90
assert(cs->cdw + 4 <= cs->
max_dw
);
in radeon_set_context_reg_rmw()
101
assert(cs->cdw + 2 + num <= cs->
max_dw
);
in radeon_set_sh_reg_seq()
119
assert(cs->cdw + 3 <= cs->
max_dw
);
in radeon_set_sh_reg_idx()
135
assert(cs->cdw + 3 <= cs->
max_dw
);
in gfx10_set_sh_reg_idx3()
146
assert(cs->cdw + 2 + num <= cs->
max_dw
);
in radeon_set_uconfig_reg_seq()
156
assert(cs->cdw + 2 + num <= cs->
max_dw
);
in radeon_set_uconfig_reg_seq_perfctr()
[all...]
H
A
D
radv_radeon_winsys.h
106
unsigned
max_dw
; /* Maximum number of dwords. */
member
H
A
D
radv_pipeline.c
6694
cs->
max_dw
= 64;
in radv_pipeline_emit_pm4()
6695
ctx_cs->
max_dw
= 256;
in radv_pipeline_emit_pm4()
6696
cs->buf = malloc(4 * (cs->
max_dw
+ ctx_cs->
max_dw
));
in radv_pipeline_emit_pm4()
6697
ctx_cs->buf = cs->buf + cs->
max_dw
;
in radv_pipeline_emit_pm4()
6730
assert(ctx_cs->cdw <= ctx_cs->
max_dw
);
in radv_pipeline_emit_pm4()
6731
assert(cs->cdw <= cs->
max_dw
);
in radv_pipeline_emit_pm4()
7218
cs->
max_dw
= pdevice->rad_info.gfx_level >= GFX10 ? 19 : 16;
in radv_compute_generate_pm4()
7219
cs->buf = malloc(cs->
max_dw
* 4);
in radv_compute_generate_pm4()
7224
assert(pipeline->base.cs.cdw <= pipeline->base.cs.
max_dw
);
in radv_compute_generate_pm4()
[all...]
H
A
D
radv_device_generated_commands.c
1298
.
max_dw
= scissor_size / 4
in radv_prepare_dgc()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H
A
D
si_pm4.c
32
if (!state->
max_dw
)
in si_pm4_cmd_begin()
33
state->
max_dw
= ARRAY_SIZE(state->pm4);
in si_pm4_cmd_begin()
34
assert(state->ndw < state->
max_dw
);
in si_pm4_cmd_begin()
42
if (!state->
max_dw
)
in si_pm4_cmd_add()
43
state->
max_dw
= ARRAY_SIZE(state->pm4);
in si_pm4_cmd_add()
44
assert(state->ndw < state->
max_dw
);
in si_pm4_cmd_add()
61
if (!state->
max_dw
)
in si_pm4_set_reg_custom()
62
state->
max_dw
= ARRAY_SIZE(state->pm4);
in si_pm4_set_reg_custom()
64
assert(state->ndw + 2 <= state->
max_dw
);
in si_pm4_set_reg_custom()
H
A
D
si_pm4.h
56
uint16_t
max_dw
;
member
H
A
D
si_cp_reg_shadowing.c
78
pm4->
max_dw
= sizeof(struct si_shadow_preamble) - offsetof(struct si_shadow_preamble, pm4.pm4);
in si_create_shadowing_ib_preamble()
H
A
D
si_build_pm4.h
57
assert(__cs->current.cdw <= __cs->current.
max_dw
); \
H
A
D
si_state.c
5568
pm4->
max_dw
= sizeof(struct si_cs_preamble) - offsetof(struct si_cs_preamble, pm4.pm4);
in si_init_cs_preamble_state()
/third_party/mesa3d/src/gallium/drivers/r600/
H
A
D
r600_cs.h
131
assert(cs->current.cdw + 2 + num <= cs->current.
max_dw
);
in radeon_set_config_reg_seq()
145
assert(cs->current.cdw + 2 + num <= cs->current.
max_dw
);
in radeon_set_context_reg_seq()
161
assert(cs->current.cdw + 3 <= cs->current.
max_dw
);
in radeon_set_context_reg_idx()
170
assert(cs->current.cdw + 2 + num <= cs->current.
max_dw
);
in radeon_set_sh_reg_seq()
184
assert(cs->current.cdw + 2 + num <= cs->current.
max_dw
);
in radeon_set_uconfig_reg_seq()
200
assert(cs->current.cdw + 3 <= cs->current.
max_dw
);
in radeon_set_uconfig_reg_idx()
H
A
D
r600_pipe.h
625
assert(cs->current.cdw + cb->num_dw <= cs->current.
max_dw
);
in r600_emit_command_buffer()
998
assert(cs->current.cdw + 2 + num <= cs->current.
max_dw
);
in radeon_set_ctl_const_seq()
H
A
D
r600_pipe_common.c
270
assert((num_dw + ctx->dma.cs.current.cdw) <= ctx->dma.cs.current.
max_dw
);
in r600_need_dma_space()
/third_party/mesa3d/src/amd/vulkan/winsys/amdgpu/
H
A
D
radv_amdgpu_cs.c
258
cs->base.
max_dw
= ib_size / 4 - 4;
in radv_amdgpu_cs_create()
270
cs->base.
max_dw
= 4096;
in radv_amdgpu_cs_create()
311
uint64_t ib_dws = MAX2(cs->base.cdw + min_size, MIN2(cs->base.
max_dw
* 2, limit_dws));
in radv_amdgpu_cs_grow()
329
cs->old_cs_buffers[cs->num_old_cs_buffers].
max_dw
= cs->base.
max_dw
;
in radv_amdgpu_cs_grow()
338
ib_dws = MAX2(cs->base.cdw + min_size, MIN2(cs->base.
max_dw
* 2, limit_dws));
in radv_amdgpu_cs_grow()
350
cs->base.
max_dw
= ib_dws;
in radv_amdgpu_cs_grow()
381
uint64_t ib_size = MAX2(min_size * 4 + 16, cs->base.
max_dw
* 4 * 2);
in radv_amdgpu_cs_grow()
421
cs->base.
max_dw
= ib_size / 4 - 4;
in radv_amdgpu_cs_grow()
435
/* Ensure that with the 4 dword reservation we subtract from
max_dw
w
in radv_amdgpu_cs_finalize()
[all...]
/third_party/mesa3d/src/gallium/winsys/radeon/drm/
H
A
D
radeon_drm_cs.c
212
rcs->current.
max_dw
= ARRAY_SIZE(cs->csc->buf);
in radeon_drm_cs_create()
468
assert(rcs->current.cdw <= rcs->current.
max_dw
);
in radeon_drm_cs_check_space()
469
return rcs->current.
max_dw
- rcs->current.cdw >= dw;
in radeon_drm_cs_check_space()
620
if (rcs->current.cdw > rcs->current.
max_dw
) {
in radeon_drm_cs_flush()
660
if (rcs->current.cdw && rcs->current.cdw <= rcs->current.
max_dw
&&
in radeon_drm_cs_flush()
/third_party/mesa3d/src/gallium/winsys/amdgpu/drm/
H
A
D
amdgpu_cs.c
825
rcs->current.
max_dw
= ib_size / 4 - amdgpu_cs_epilog_dws(cs);
in amdgpu_get_new_ib()
1098
assert(rcs->current.cdw <= rcs->current.
max_dw
);
in amdgpu_cs_check_space()
1106
if (rcs->current.
max_dw
- rcs->current.cdw >= dw)
in amdgpu_cs_check_space()
1141
rcs->current.
max_dw
+= cs_epilog_dw;
in amdgpu_cs_check_space()
1155
assert(rcs->current.cdw <= rcs->current.
max_dw
);
in amdgpu_cs_check_space()
1164
rcs->prev[rcs->num_prev].
max_dw
= rcs->current.cdw; /* no modifications */
in amdgpu_cs_check_space()
1171
rcs->current.
max_dw
= ib->big_ib_buffer->size / 4 - cs_epilog_dw;
in amdgpu_cs_check_space()
1699
rcs->current.
max_dw
+= amdgpu_cs_epilog_dws(cs);
in amdgpu_cs_flush()
1745
if (rcs->current.cdw > rcs->current.
max_dw
) {
in amdgpu_cs_flush()
1751
rcs->current.cdw <= rcs->current.
max_dw
in amdgpu_cs_flush()
[all...]
/third_party/mesa3d/src/amd/vulkan/winsys/null/
H
A
D
radv_null_cs.c
78
cs->base.
max_dw
= 4096;
in radv_null_cs_create()
/third_party/mesa3d/src/gallium/drivers/r300/
H
A
D
r300_cs.h
49
assert(size <= (cs_copy->current.
max_dw
- cs_copy->current.cdw)); \
/third_party/mesa3d/src/gallium/include/winsys/
H
A
D
radeon_winsys.h
192
unsigned
max_dw
; /* Maximum number of dwords. */
member
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