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/third_party/ffmpeg/libavcodec/arm/
H A Didctdsp_arm.S32 ldrsh r5, [r0]
33 ldrsh r7, [r0, #2]
47 ldrsh r5, [r0, #4] /* moved form [A] */
51 ldrsh r7, [r0, #6]
68 ldrsh r5, [r0, #8] /* moved form [C] */
75 ldrsh r7, [r0, #10]
89 ldrsh r5, [r0, #12] /* moved from [D] */
93 ldrsh r7, [r0, #14]
H A Djrevdct_arm.S65 ldrsh r0, [lr, # 0] @ r0 = 'd0'
66 ldrsh r2, [lr, # 2] @ r2 = 'd2'
81 ldrsh r1, [lr, # 8] @ r1 = 'd1'
82 ldrsh r4, [lr, # 4] @ r4 = 'd4'
83 ldrsh r6, [lr, # 6] @ r6 = 'd6'
102 ldrsh r3, [lr, #10] @ r3 = 'd3'
103 ldrsh r5, [lr, #12] @ r5 = 'd5'
104 ldrsh r7, [lr, #14] @ r7 = 'd7'
212 ldrsh r0, [lr, #( 0*8)] @ r0 = 'd0'
213 ldrsh r
[all...]
H A Dac3dsp_armv6.S38 ldrsh r9, [r0], #2 @ mask[band]
57 ldrsh r8, [r1], #2
58 ldrsh lr, [r1], #2
73 ldrsh r8, [r1], #2 @ psd[bin]
H A Dmpegvideo_armv5te_s.S97 ldrsh r9, [r0, #0]
98 ldrsh lr, [r0, #2]
H A Dsimple_idct_arm.S82 ldrsh r6, [r14, #0] @ R6=ROWr16[0]
171 ldrsh r4, [r14, #4] @ R4=ROWr16[2] (a3 not defined yet)
197 ldrsh r11, [r14, #8] @ R11=ROWr16[4]
202 ldrsh r9, [r14, #12] @ R9=ROWr16[6]
311 ldrsh r7, [r14, #16]
318 ldrsh r2, [r14, #48]
340 ldrsh r3, [r14, #80] @ R3=COLr16[5x8]
347 ldrsh r4, [r14, #112] @ R4=COLr16[7x8]
371 ldrsh r6, [r14, #0]
375 ldrsh r
[all...]
H A Dhevcdsp_idct_neon.S234 ldrsh r1, [r0]
249 ldrsh r1, [r0]
270 ldrsh r1, [r0]
294 ldrsh r1, [r0]
H A Dh264idct_neon.S112 ldrsh lr, [r1]
141 ldrsh r8, [r1]
169 ldrsh r8, [r1]
389 ldrsh lr, [r1]
H A Dmpegvideo_neon.S88 ldrsh r4, [r1]
H A Dvp3dsp_neon.S354 ldrsh r12, [r2]
H A Dvp8dsp_armv6.S184 ldrsh r2, [r1]
321 ldrsh r3, [r1]
/third_party/ffmpeg/libavcodec/aarch64/
H A Dh264idct_neon.S121 ldrsh w3, [x1]
148 ldrsh w3, [x1]
179 ldrsh w3, [x1] // block[i*16]
393 ldrsh w11, [x1]
H A Dhevcdsp_sao_neon.S42 0: ldrsh x9, [x4, x8, lsl #1] // sao_offset_val[k+1]
H A Dvc1dsp_neon.S543 ldrsh w2, [x2]
595 ldrsh w2, [x2]
631 ldrsh w2, [x2]
675 ldrsh w2, [x2]
/third_party/vixl/test/aarch64/
H A Dtest-disasm-aarch64.cc1250 COMPARE(ldrsh(w0, MemOperand(x1)), "ldrsh w0, [x1]"); in TEST()
1251 COMPARE(ldrsh(w2, MemOperand(x3, 8)), "ldrsh w2, [x3, #8]"); in TEST()
1252 COMPARE(ldrsh(w4, MemOperand(x5, 42, PreIndex)), "ldrsh w4, [x5, #42]!"); in TEST()
1253 COMPARE(ldrsh(x6, MemOperand(x7, -11, PostIndex)), "ldrsh x6, [x7], #-11"); in TEST()
1254 COMPARE(ldrsh(w8, MemOperand(x9, 0, PreIndex)), "ldrsh w in TEST()
[all...]
H A Dtest-cpu-features-aarch64.cc318 TEST_NONE(ldrsh_0, ldrsh(w0, MemOperand(x1, 11, PostIndex)))
319 TEST_NONE(ldrsh_1, ldrsh(w0, MemOperand(x1, -34, PreIndex)))
320 TEST_NONE(ldrsh_2, ldrsh(w0, MemOperand(x1, 6212)))
321 TEST_NONE(ldrsh_3, ldrsh(x0, MemOperand(x1, -78, PostIndex)))
322 TEST_NONE(ldrsh_4, ldrsh(x0, MemOperand(x1, 72, PreIndex)))
323 TEST_NONE(ldrsh_5, ldrsh(x0, MemOperand(x1, 6232)))
324 TEST_NONE(ldrsh_6, ldrsh(w0, MemOperand(x1, w2, UXTW, 0)))
325 TEST_NONE(ldrsh_7, ldrsh(w0, MemOperand(x1, x2, LSL, 0)))
326 TEST_NONE(ldrsh_8, ldrsh(x0, MemOperand(x1, w2, SXTW, 0)))
327 TEST_NONE(ldrsh_9, ldrsh(x
[all...]
H A Dtest-trace-aarch64.cc202 __ ldrsh(w9, MemOperand(x0)); in GenerateTestSequenceBase()
203 __ ldrsh(w9, MemOperand(x1, 2, PostIndex)); in GenerateTestSequenceBase()
204 __ ldrsh(w9, MemOperand(x1, 2, PreIndex)); in GenerateTestSequenceBase()
205 __ ldrsh(x10, MemOperand(x0)); in GenerateTestSequenceBase()
206 __ ldrsh(x10, MemOperand(x1, 2, PostIndex)); in GenerateTestSequenceBase()
207 __ ldrsh(x10, MemOperand(x1, 2, PreIndex)); in GenerateTestSequenceBase()
379 __ ldrsh(xzr, MemOperand(sp, 16, PostIndex)); in GenerateTestSequenceBase()
/third_party/vixl/src/aarch32/
H A Dassembler-aarch32.h2533 void ldrsh(Condition cond,
2537 void ldrsh(Register rt, const MemOperand& operand) { in ldrsh() function in vixl::aarch32::Assembler
2538 ldrsh(al, Best, rt, operand); in ldrsh()
2540 void ldrsh(Condition cond, Register rt, const MemOperand& operand) { in ldrsh() function in vixl::aarch32::Assembler
2541 ldrsh(cond, Best, rt, operand); in ldrsh()
2543 void ldrsh(EncodingSize size, Register rt, const MemOperand& operand) { in ldrsh() function in vixl::aarch32::Assembler
2544 ldrsh(al, size, rt, operand); in ldrsh()
2547 void ldrsh(Condition cond, Register rt, Location* location);
2552 void ldrsh(Register rt, Location* location) { ldrsh(a function in vixl::aarch32::Assembler
[all...]
H A Dmacro-assembler-aarch32.cc1684 ldrsh(rt, MemOperandComputationHelper(cond, scratch, location, mask)); in Delegate()
H A Ddisasm-aarch32.cc1825 void Disassembler::ldrsh(Condition cond, in ldrsh() function in vixl::aarch32::Disassembler
1834 void Disassembler::ldrsh(Condition cond, Register rt, Location* location) { in ldrsh() function in vixl::aarch32::Disassembler
7882 ldrsh(CurrentCond(), in DecodeT32()
17965 ldrsh(CurrentCond(), in DecodeT32()
17970 ldrsh(CurrentCond(), Register(rt), &location); in DecodeT32()
18000 ldrsh(CurrentCond(), in DecodeT32()
18009 ldrsh(CurrentCond(), in DecodeT32()
18037 ldrsh(CurrentCond(), in DecodeT32()
18060 ldrsh(CurrentCond(), in DecodeT32()
18094 ldrsh(CurrentCon in DecodeT32()
[all...]
H A Ddisasm-aarch32.h892 void ldrsh(Condition cond,
897 void ldrsh(Condition cond, Register rt, Location* location);
/third_party/node/deps/v8/src/codegen/arm/
H A Dassembler-arm.h607 void ldrsh(Register dst, const MemOperand& src, Condition cond = al);
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/DartARM32/
H A Dassembler_arm.h559 void ldrsh(Register rd, Address ad, Condition cond = AL);
H A Dassembler_arm.cc494 void Assembler::ldrsh(Register rd, Address ad, Condition cond) {
2719 ldrsh(reg, Address(base, offset), cond);
/third_party/node/deps/v8/src/codegen/arm64/
H A Dassembler-arm64.h826 void ldrsh(const Register& rt, const MemOperand& src);
/third_party/vixl/test/aarch32/
H A Dtest-assembler-cond-rd-memop-immediate-512-a32.cc53 M(ldrsh) \
3605 #include "aarch32/traces/assembler-cond-rd-memop-immediate-512-ldrsh-a32.h"

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