| /third_party/vixl/test/aarch64/ |
| H A D | test-disasm-aarch64.cc | 1593 COMPARE(ldpsw(x0, x1, MemOperand(x2)), "ldpsw x0, x1, [x2]"); in TEST()
1594 COMPARE(ldpsw(x3, x4, MemOperand(x5, 16)), "ldpsw x3, x4, [x5, #16]"); in TEST()
1595 COMPARE(ldpsw(x6, x7, MemOperand(x8, -32, PreIndex)), in TEST()
1596 "ldpsw x6, x7, [x8, #-32]!"); in TEST()
1597 COMPARE(ldpsw(x9, x10, MemOperand(x11, 128, PostIndex)), in TEST()
1598 "ldpsw x9, x10, [x11], #128"); in TEST()
1599 COMPARE(ldpsw(x0, x1, MemOperand(x10, 0, PreIndex)), in TEST()
1600 "ldpsw x in TEST()
[all...] |
| H A D | test-trace-aarch64.cc | 175 __ ldpsw(x27, x28, MemOperand(x0)); in GenerateTestSequenceBase()
176 __ ldpsw(x27, x28, MemOperand(x1, 8, PostIndex)); in GenerateTestSequenceBase()
177 __ ldpsw(x27, x28, MemOperand(x1, 8, PreIndex)); in GenerateTestSequenceBase()
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| H A D | test-cpu-features-aarch64.cc | 286 TEST_NONE(ldpsw_0, ldpsw(x0, x1, MemOperand(x2, -212)))
287 TEST_NONE(ldpsw_1, ldpsw(x0, x1, MemOperand(x2, -36, PostIndex)))
288 TEST_NONE(ldpsw_2, ldpsw(x0, x1, MemOperand(x2, 104, PreIndex)))
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| H A D | test-assembler-aarch64.cc | 11691 __ ldpsw(x2, x3, MemOperand(x0, offset));
11910 __ ldpsw(x2, x3, MemOperand(x0, preindex, PreIndex));
12077 __ ldpsw(x2, x3, MemOperand(x0, postindex, PostIndex));
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 837 void ldpsw(const Register& rt, const Register& rt2, const MemOperand& src);
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| H A D | assembler-arm64.cc | 1237 void Assembler::ldpsw(const Register& rt, const Register& rt2, in ldpsw() function in v8::internal::Assembler
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| /third_party/vixl/src/aarch64/ |
| H A D | assembler-aarch64.h | 1298 void ldpsw(const Register& xt, const Register& xt2, const MemOperand& src);
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| H A D | assembler-aarch64.cc | 1111 void Assembler::ldpsw(const Register& xt, in ldpsw() function in vixl::aarch64::Assembler
1148 // Only X registers may be specified for ldpsw. in LoadStorePair()
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