| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 1064 __ ld3r(v24.V16B(), v25.V16B(), v26.V16B(), MemOperand(x0)); in GenerateTestSequenceNEON()
1065 __ ld3r(v24.V16B(), v25.V16B(), v26.V16B(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON()
1066 __ ld3r(v3.V16B(), v4.V16B(), v5.V16B(), MemOperand(x1, 3, PostIndex)); in GenerateTestSequenceNEON()
1067 __ ld3r(v4.V1D(), v5.V1D(), v6.V1D(), MemOperand(x0)); in GenerateTestSequenceNEON()
1068 __ ld3r(v7.V1D(), v8.V1D(), v9.V1D(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON()
1069 __ ld3r(v17.V1D(), v18.V1D(), v19.V1D(), MemOperand(x1, 24, PostIndex)); in GenerateTestSequenceNEON()
1070 __ ld3r(v16.V2D(), v17.V2D(), v18.V2D(), MemOperand(x0)); in GenerateTestSequenceNEON()
1071 __ ld3r(v20.V2D(), v21.V2D(), v22.V2D(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON()
1072 __ ld3r(v14.V2D(), v15.V2D(), v16.V2D(), MemOperand(x1, 24, PostIndex)); in GenerateTestSequenceNEON()
1073 __ ld3r(v1 in GenerateTestSequenceNEON()
[all...] |
| H A D | test-cpu-features-aarch64.cc | 1181 TEST_NEON(ld3r_0, ld3r(v0.V8B(), v1.V8B(), v2.V8B(), MemOperand(x3)))
1182 TEST_NEON(ld3r_1, ld3r(v0.V16B(), v1.V16B(), v2.V16B(), MemOperand(x3)))
1183 TEST_NEON(ld3r_2, ld3r(v0.V4H(), v1.V4H(), v2.V4H(), MemOperand(x3)))
1184 TEST_NEON(ld3r_3, ld3r(v0.V8H(), v1.V8H(), v2.V8H(), MemOperand(x3)))
1185 TEST_NEON(ld3r_4, ld3r(v0.V2S(), v1.V2S(), v2.V2S(), MemOperand(x3)))
1186 TEST_NEON(ld3r_5, ld3r(v0.V4S(), v1.V4S(), v2.V4S(), MemOperand(x3)))
1187 TEST_NEON(ld3r_6, ld3r(v0.V1D(), v1.V1D(), v2.V1D(), MemOperand(x3)))
1188 TEST_NEON(ld3r_7, ld3r(v0.V2D(), v1.V2D(), v2.V2D(), MemOperand(x3)))
1190 ld3r(v0.V8B(), v1.V8B(), v2.V8B(), MemOperand(x3, 3, PostIndex)))
1192 ld3r(v
[all...] |
| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1876 void ld3r(const VRegister& vt, const VRegister& vt2, const VRegister& vt3,
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| H A D | macro-assembler-arm64.h | 1684 ld3r(vt, vt2, vt3, src); in Ld3r()
|
| H A D | assembler-arm64.cc | 2416 void Assembler::ld3r(const VRegister& vt, const VRegister& vt2, in ld3r() function in v8::internal::Assembler
|
| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 1562 void ld3r(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2,
|
| H A D | simulator-arm64.cc | 5106 ld3r(vf, vreg(rt), vreg(rt2), vreg(rt3), addr);
|
| H A D | simulator-logic-arm64.cc | 431 void Simulator::ld3r(VectorFormat vform, LogicVRegister dst1, in ld3r() function in v8::internal::Simulator
|
| /third_party/vixl/src/aarch64/ |
| H A D | simulator-aarch64.h | 3353 void ld3r(VectorFormat vform,
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| H A D | assembler-aarch64.h | 2922 void ld3r(const VRegister& vt,
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| H A D | assembler-aarch64.cc | 2689 void Assembler::ld3r(const VRegister& vt, in ld3r() function in vixl::aarch64::Assembler
|
| H A D | logic-aarch64.cc | 307 void Simulator::ld3r(VectorFormat vform, in ld3r() function in vixl::aarch64::Simulator
|
| H A D | macro-assembler-aarch64.h | 3425 ld3r(vt, vt2, vt3, src); in Ld3r()
|
| H A D | simulator-aarch64.cc | 8537 ld3r(vf, in Simulator()
|