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Searched refs:kFormatVnB (Results 1 - 7 of 7) sorted by relevance

/third_party/vixl/src/aarch64/
H A Dinstructions-aarch64.cc561 // For .h, index uses bit zero of the size field, so kFormatVnB below implies in GetSVEMulZmAndIndex()
570 case kFormatVnB: in GetSVEMulZmAndIndex()
1021 return kFormatVnB; in VectorFormatHalfWidth()
1047 case kFormatVnB: in VectorFormatDoubleWidth()
1099 return kFormatVnB; in VectorFormatHalfWidthDoubleLanes()
1161 case kFormatVnB: in IsSVEFormat()
1177 return kFormatVnB; in SVEFormatFromLaneSizeInBytes()
1268 case kFormatVnB: in LaneSizeInBitsFromFormat()
1308 case kFormatVnB: in LaneSizeInBytesLog2FromFormat()
H A Dsimulator-aarch64.cc836 dup_immediate(kFormatVnB, ones, 0xff); in Simulator()
837 mov_zeroing(kFormatVnB, result, pg, ones); in Simulator()
845 dup_immediate(kFormatVnB, zero, 0); in Simulator()
1234 case kFormatVnB: in Simulator()
2203 ext(kFormatVnB, zd, zn, zn2, index); in Simulator()
2213 if (instr->GetSVEVectorFormat() == kFormatVnB) { in Simulator()
2214 histogram(kFormatVnB, in Simulator()
2225 pmul(kFormatVnB, zd, zn, zm); in Simulator()
2240 if (vform == kFormatVnB) vform = kFormatVnH; in Simulator()
2259 if (vform == kFormatVnB) vfor in Simulator()
[all...]
H A Ddisasm-aarch64.cc3999 if (instr->GetSVEVectorFormat() != kFormatVnB) { in Disassembler()
4069 if ((instr->GetSVEVectorFormat() == kFormatVnB) && in Disassembler()
4312 if (instr->GetSVEVectorFormat() != kFormatVnB) { in Disassembler()
4414 if (instr->GetSVEVectorFormat() == kFormatVnB) { in Disassembler()
4433 if (instr->GetSVEVectorFormat() == kFormatVnB) { in Disassembler()
4513 if (instr->GetSVEVectorFormat() == kFormatVnB) { in Disassembler()
5151 if (instr->GetSVEVectorFormat() == kFormatVnB) { in Disassembler()
5159 if (instr->GetSVEVectorFormat() == kFormatVnB) { in Disassembler()
5167 if (instr->GetSVEVectorFormat() == kFormatVnB) { in Disassembler()
5175 if (instr->GetSVEVectorFormat() == kFormatVnB) { in Disassembler()
[all...]
H A Dlogic-aarch64.cc2529 return ext(kFormatVnB, dst, src, src, index);
6059 mov(kFormatVnB, tmp, src);
6414 int first_pg = GetFirstActive(kFormatVnB, pg);
6415 VIXL_ASSERT(first_pg < LaneCountFromFormat(kFormatVnB));
6417 if (first_pg >= 0) dst.SetActive(kFormatVnB, first_pg, true);
6606 dup_immediate(kFormatVnB, zero, 0);
7363 for (int i = 0; i < LaneCountFromFormat(kFormatVnB); i++) {
7364 if (pg.IsActive(kFormatVnB, i)) {
7365 pd.SetActive(kFormatVnB, i, !break_);
7366 break_ |= pn.IsActive(kFormatVnB,
[all...]
H A Dinstructions-aarch64.h213 kFormatVnB = SVE_B | kFormatSVE, enumerator
329 return kFormatVnB; in GetSVEVectorFormat()
/third_party/vixl/test/aarch64/
H A Dtest-api-aarch64.cc296 VIXL_CHECK(ZRegister(0, kFormatVnB).Is(z0.VnB())); in TEST()
311 VIXL_CHECK(PRegisterWithLaneSize(0, kFormatVnB).Is(p0.VnB())); in TEST()
1566 temps.Include(ZRegister(17, kFormatVnB)); in TEST()
1598 temps.Exclude(ZRegister(17, kFormatVnB)); in TEST()
1651 temps.Include(PRegisterWithLaneSize(12, kFormatVnB)); in TEST()
1683 temps.Exclude(PRegisterWithLaneSize(12, kFormatVnB)); in TEST()
H A Dtest-trace-aarch64.cc3081 reg.SetActive(kFormatVnB, bit, ((bit + 1) % (r + 2)) != 0);

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