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Searched refs:instrs (Results 1 - 25 of 28) sorted by relevance

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/third_party/mesa3d/src/freedreno/afuc/
H A Ddisasm.c289 disasm_instr(uint32_t *instrs, unsigned pc) in disasm_instr() argument
292 afuc_instr *instr = (void *)&instrs[pc]; in disasm_instr()
331 printf("\t%04x: %08x ", pc, instrs[pc]); in disasm_instr()
342 if (instrs[pc] != nop) { in disasm_instr()
343 printerr("[%08x]", instrs[pc]); in disasm_instr()
349 print_gpu_reg(instrs[pc]); in disasm_instr()
377 print_alu_name(opc, instrs[pc]); in disasm_instr()
453 printf("[%08x] ; ", instrs[pc]); in disasm_instr()
470 print_alu_name(instr->alu.alu, instrs[pc]); in disasm_instr()
665 printf("[%08x] ; ", instrs[p in disasm_instr()
724 setup_labels(uint32_t *instrs, uint32_t sizedwords) setup_labels() argument
837 uint32_t *instrs = buf; disasm_legacy() local
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H A Demu.c314 afuc_instr *instr = (void *)&emu->instrs[emu->gpr_regs.pc]; in emu_step()
449 mem_write_dword(emu, EMU_INSTR_BASE + (4 * i), emu->instrs[i]); in emu_init()
472 uint32_t *instrs = emu->instrs; in emu_fini() local
479 emu->instrs = instrs; in emu_fini()
H A Dparser.y171 %start instrs
175 instrs: instr_or_label instrs label
H A Demu.h160 uint32_t *instrs; member
/third_party/mesa3d/src/panfrost/bifrost/
H A Ddisassemble.c444 struct bifrost_alu_inst instrs[8] = {}; in dump_clause() local
482 instrs[idx + 1] = main_instr; in dump_clause()
483 instrs[idx].add_bits = bits(words[3], 0, 17) | ((tag & 0x7) << 17); in dump_clause()
484 instrs[idx].fma_bits |= bits(words[2], 19, 32) << 10; in dump_clause()
494 instrs[1] = main_instr; in dump_clause()
500 instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17; in dump_clause()
501 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10; in dump_clause()
511 instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17; in dump_clause()
512 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10; in dump_clause()
514 instrs[ in dump_clause()
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/third_party/mesa3d/src/amd/compiler/
H A Daco_form_hard_clauses.cpp42 emit_clause(Builder& bld, unsigned num_instrs, aco_ptr<Instruction>* instrs) in emit_clause() argument
47 for (; (start < num_instrs) && instrs[start]->definitions.empty(); start++) in emit_clause()
48 bld.insert(std::move(instrs[start])); in emit_clause()
51 for (; (end < num_instrs) && !instrs[end]->definitions.empty(); end++) in emit_clause()
59 bld.insert(std::move(instrs[i])); in emit_clause()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_nir_optim.c56 struct set *instrs = _mesa_set_create(NULL, _mesa_hash_pointer, in check_instr_depends_on_tex() local
60 _mesa_set_add(instrs, &store->instr); in check_instr_depends_on_tex()
65 if (_mesa_set_search(instrs, instr)) in check_instr_depends_on_tex()
68 _mesa_set_add(instrs, instr); in check_instr_depends_on_tex()
91 _mesa_set_destroy(instrs, NULL); in check_instr_depends_on_tex()
/third_party/mesa3d/src/freedreno/decode/
H A Dpgmdump.c542 uint8_t *instrs = NULL; in dump_shaders_a3xx() local
562 instrs = &vs_hdr[n]; in dump_shaders_a3xx()
572 instrs = ptr; in dump_shaders_a3xx()
597 dump_hex(instrs, instrs_size); in dump_shaders_a3xx()
605 instrs += ALIGN(instrs_size, 8) - instrs_size; in dump_shaders_a3xx()
608 instrs += 32; in dump_shaders_a3xx()
612 disasm_a3xx((uint32_t *)instrs, instrs_size / 4, level + 1, stdout, in dump_shaders_a3xx()
614 dump_raw_shader((uint32_t *)instrs, instrs_size / 4, i, "vo3"); in dump_shaders_a3xx()
623 uint8_t *instrs = NULL; in dump_shaders_a3xx() local
642 instrs in dump_shaders_a3xx()
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/third_party/mesa3d/src/freedreno/isa/
H A Dencode.c328 BITSET_WORD *ptr, *instrs; in isa_assemble() local
332 ptr = instrs = rzalloc_size(v, info->size); in isa_assemble()
343 store_instruction(instrs, encoded); in isa_assemble()
344 instrs += BITMASK_WORDS; in isa_assemble()
/third_party/mesa3d/src/compiler/nir/
H A Dnir_opt_gcm.c91 struct exec_list instrs; member
313 /* Index the instructions for use in gcm_state::instrs */ in gcm_pin_instructions()
400 * the program and put it on the instrs list. This has a couple in gcm_pin_instructions()
411 exec_list_push_tail(&state->instrs, &instr->node); in gcm_pin_instructions()
813 exec_list_make_empty(&state.instrs); in opt_gcm_impl()
825 foreach_list_typed_safe(nir_instr, instr, node, &state.instrs) { in opt_gcm_impl()
835 foreach_list_typed(nir_instr, instr, node, &state.instrs) in opt_gcm_impl()
838 foreach_list_typed(nir_instr, instr, node, &state.instrs) in opt_gcm_impl()
841 while (!exec_list_is_empty(&state.instrs)) { in opt_gcm_impl()
843 state.instrs in opt_gcm_impl()
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/third_party/node/deps/v8/src/heap/base/asm/x64/
H A Dpush_registers_masm.S32 ;; Use aligned instrs as we are certain that the stack is properly aligned.
/third_party/mesa3d/src/panfrost/midgard/
H A Dmidgard_ra.c360 midgard_instruction *instrs[2][4]; in mir_compute_interference() local
366 instrs[0][instr_count[0]++] = bundle->instructions[i]; in mir_compute_interference()
368 instrs[1][instr_count[1]++] = bundle->instructions[i]; in mir_compute_interference()
373 midgard_instruction *ins_a = instrs[i][j]; in mir_compute_interference()
378 midgard_instruction *ins_b = instrs[i][k]; in mir_compute_interference()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonBranchRelaxation.cpp115 for (auto &MI : B.instrs()) { in computeOffset()
/third_party/mesa3d/src/mesa/program/
H A Dprogram.c445 struct prog_instruction *instrs = prog->arb.Instructions; in _mesa_add_separate_state_parameters() local
449 struct prog_instruction *inst = instrs + i; in _mesa_add_separate_state_parameters()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DUnreachableBlockElim.cpp153 for (auto &I : DeadBlocks[i]->instrs()) in runOnMachineFunction()
H A DMIRCanonicalizerPass.cpp308 for (MachineInstr &MI : MBB->instrs()) { in propagateLocalCopies()
H A DMachineBasicBlock.cpp410 for (const MachineInstr &MI : instrs()) {
973 for (MachineInstr &MI : NMBB->instrs()) {
H A DBranchFolding.cpp1313 for (MachineInstr &MI : MBB.instrs()) in copyDebugInfoToPredecessor()
1325 for (MachineInstr &MI : MBB.instrs()) in copyDebugInfoToSuccessor()
H A DLiveDebugValues.cpp1544 if (none_of(MBB.instrs(), hasNonArtificialLocation)) in ExtendRanges()
/third_party/mesa3d/src/compiler/isaspec/
H A Ddecode.c711 BITSET_WORD *instrs = bin; in decode() local
719 next_instruction(&instr, &instrs[state->n * BITMASK_WORDS]); in decode()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
H A DMachineBasicBlock.h211 instr_range instrs() { return instr_range(instr_begin(), instr_end()); } in instrs() function in llvm::MachineBasicBlock
212 const_instr_range instrs() const { in instrs() function in llvm::MachineBasicBlock
/third_party/elfutils/libcpu/
H A Di386_parse.y245 spec: masks kPERCPERC '\n' instrs
280 instrs: instrs '\n' instr label
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
H A DPPCReduceCRLogicals.cpp58 for (auto &MI : Successor->instrs()) { in updatePHIs()
91 for (auto &MI : Successor->instrs()) { in addIncomingValuesToPHIs()
/third_party/mesa3d/src/freedreno/ir3/
H A Dir3_parser.y689 shader: { new_shader(); } headers instrs
797 instrs: instrs instr label
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DGCNRegBankReassign.cpp694 for (MachineInstr &MI : MBB.instrs()) {

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