Home
last modified time | relevance | path

Searched refs:index_reg (Results 1 - 18 of 18) sorted by relevance

/third_party/mesa3d/src/panfrost/midgard/
H A Ddisassemble.c1419 print_ldst_read_reg(fp, word->index_reg); in print_load_store_instr()
1441 word->index_reg != 0x7) { in print_load_store_instr()
1445 print_ldst_read_reg(fp, word->index_reg); in print_load_store_instr()
1477 print_ldst_read_reg(fp, word->index_reg); in print_load_store_instr()
1484 print_ldst_read_reg(fp, word->index_reg); in print_load_store_instr()
1519 if (word->index_reg == 0x7 && ctx->midg_stats.varying_count >= 0) in print_load_store_instr()
1525 if (word->index_reg == 0x7 && ctx->midg_stats.attribute_count >= 0) in print_load_store_instr()
H A Dmidgard_compile.c1239 ins.load_store.index_reg = REGISTER_LDST_ZERO; in emit_ubo_read()
1451 ins.load_store.index_reg = REGISTER_LDST_ZERO; in emit_varying_read()
1538 ins.load_store.index_reg = REGISTER_LDST_ZERO; in emit_image_op()
1553 ins.load_store.index_reg = REGISTER_LDST_ZERO; in emit_attr_read()
1710 ld.load_store.index_reg = REGISTER_LDST_ZERO; in emit_special()
1900 ld.load_store.index_reg = target >> 2; in emit_intrinsic()
1916 ld.load_store.index_reg = REGISTER_LDST_ZERO; in emit_intrinsic()
1936 ld.load_store.index_reg = index >> 2; in emit_intrinsic()
1947 ld.load_store.index_reg = REGISTER_LDST_ZERO; in emit_intrinsic()
2031 st.load_store.index_reg in emit_intrinsic()
[all...]
H A Dmidgard_address.c277 ins->load_store.index_reg = REGISTER_LDST_ZERO; in mir_set_offset()
H A Dmidgard_emit.c617 ldst.index_reg = SSA_REG_FROM_FIXED(ins->src[2]) - REGISTER_LDST_BASE; in load_store_from_instr()
619 ldst.index_comp = midgard_ldst_comp(ldst.index_reg, ins->swizzle[2][0], sz); in load_store_from_instr()
H A Dmidgard.h763 * For cmpxchg, index_reg is used for the comparison value.
768 unsigned index_reg : 3; member
H A Dcompiler.h585 .index_reg = REGISTER_LDST_ZERO, in v_load_store_scratch()
H A Dmidgard_ra.c1122 .index_reg = REGISTER_LDST_ZERO, in mir_demote_uniforms()
/third_party/mesa3d/src/gallium/drivers/r600/sfn/
H A Dsfn_instr_export.h176 unsigned index_reg() const {assert(m_export_index->sel() >= 0); return m_export_index->sel();} in index_reg() function in r600::MemRingOutInstr
H A Dsfn_assembler.cpp611 output.index_gpr = instr.index_reg(); in visit()
985 m_bc->index_reg[idx] != (unsigned)addr.sel() in emit_index_reg()
1033 m_bc->index_reg[idx] = addr.sel(); in emit_index_reg()
1123 if (m_bc->index_reg[1] == dst.sel && in copy_dst()
1127 if (m_bc->index_reg[0] == dst.sel && in copy_dst()
/third_party/mesa3d/src/gallium/drivers/r600/
H A Dr600_asm.h281 unsigned index_reg[2]; /* indexing register CF_INDEX_[01] */ member
H A Deg_asm.c191 alu.src[0].sel = bc->index_reg[id]; in egcm_load_index_reg()
H A Dr600_shader.c941 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg; in get_address_file_reg()
1951 /* pull the value from index_reg */ in fetch_gs_input()
2074 /* pull the value from index_reg */ in r600_get_byte_address()
2114 /* pull the value from index_reg */ in r600_get_byte_address()
3651 ctx.bc->index_reg[0] = ++regno; in r600_shader_from_tgsi()
3652 ctx.bc->index_reg[1] = ++regno; in r600_shader_from_tgsi()
8846 /* ADDR[1,2] are stored in index_reg[0,1] on EG, and can be used for indexing
/third_party/vixl/src/aarch64/
H A Dlogic-aarch64.cc5707 LogicVRegister index_reg = dup_element(kFormat8H, temp, src2, index);
5708 fmul<SimFloat16>(vform, dst, src1, index_reg);
5710 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index);
5711 fmul<float>(vform, dst, src1, index_reg);
5714 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index);
5715 fmul<double>(vform, dst, src1, index_reg);
5729 LogicVRegister index_reg = dup_element(kFormat8H, temp, src2, index);
5730 fmla<SimFloat16>(vform, dst, dst, src1, index_reg);
5732 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index);
5733 fmla<float>(vform, dst, dst, src1, index_reg);
[all...]
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-logic-arm64.cc3671 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); in fmul() local
3672 fmul<float>(vform, dst, src1, index_reg); in fmul()
3675 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index); in fmul() local
3676 fmul<double>(vform, dst, src1, index_reg); in fmul()
3687 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); in fmla() local
3688 fmla<float>(vform, dst, src1, index_reg); in fmla()
3691 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index); in fmla() local
3692 fmla<double>(vform, dst, src1, index_reg); in fmla()
3703 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); in fmls() local
3704 fmls<float>(vform, dst, src1, index_reg); in fmls()
3707 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index); fmls() local
3719 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); fmulx() local
3724 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index); fmulx() local
[all...]
/third_party/node/deps/v8/src/wasm/baseline/
H A Dliftoff-compiler.cc4634 Register index_reg =
4637 if (index_reg == no_reg) return;
4638 LiftoffRegList pinned = {index_reg};
4639 AlignmentCheckMem(decoder, value_kind_size(kind), imm.offset, index_reg,
4644 __ cache_state()->is_used(LiftoffRegister(index_reg))
4646 : index_reg;
4648 __ emit_ptrsize_zeroextend_i32(index_plus_offset, index_reg);
4682 Register index_reg = BoundsCheckMem(decoder, kInt32Size, imm.offset,
4684 if (index_reg == no_reg) return;
4685 LiftoffRegList pinned = {index_reg};
[all...]
/third_party/mesa3d/src/intel/compiler/
H A Dbrw_vec4_generator.cpp814 struct brw_reg index_reg = brw_vec1_grf( in generate_tcs_input_urb_offsets() local
818 retype(index_reg, BRW_REGISTER_TYPE_UD)); in generate_tcs_input_urb_offsets()
/third_party/pcre2/pcre2/src/
H A Dpcre2_jit_simd_inc.h1142 sljit_s32 base_reg, sljit_s32 index_reg)
1146 instruction[0] = (sljit_u16)(0xe700 | (dst_vreg << 4) | index_reg);
/third_party/node/deps/v8/src/execution/s390/
H A Dsimulator-s390.cc2982 #define GET_ADDRESS(index_reg, base_reg, offset) \
2983 (((index_reg) == 0) ? 0 : get_register(index_reg)) + \

Completed in 67 milliseconds