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/third_party/mesa3d/src/asahi/compiler/
H A Dagx_opcodes.py29 def __init__(self, name, dests, srcs, imms, is_float, can_eliminate, encoding_16, encoding_32):
33 self.imms = imms
60 def op(name, encoding_32, dests = 1, srcs = 0, imms = [], is_float = False, can_eliminate = True, encoding_16 = None):
64 opcodes[name] = Opcode(name, dests, srcs, imms, is_float, can_eliminate, encoding_16, encoding_32)
164 imms = [IMM]) variable
168 srcs = 2, imms = [SHIFT])
172 srcs = 3, imms = [SHIFT])
176 srcs = 3, imms = [BFI_MASK])
180 srcs = 3, imms
234 imms = [NEST, FCOND if is_float else ICOND, INVERT_COND] global() variable
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/third_party/mesa3d/src/gallium/drivers/r300/compiler/
H A Dradeon_dataflow_swizzles.c101 float imms[4] = {0.0f, 0.0f, 0.0f, 0.0f}; in try_rewrite_constant() local
389 imms[new_swz] = 0.0f; in try_rewrite_constant()
393 imms[new_swz] = -0.5f; in try_rewrite_constant()
395 imms[new_swz] = 0.5f; in try_rewrite_constant()
400 imms[new_swz] = -1.0f; in try_rewrite_constant()
402 imms[new_swz] = 1.0f; in try_rewrite_constant()
406 imms[new_swz] = rc_get_constant_value(c, reg->Index, in try_rewrite_constant()
412 imms); in try_rewrite_constant()
/third_party/mesa3d/src/gallium/auxiliary/translate/
H A Dtranslate_sse.c489 unsigned imms[2] = { 0, 0x3f800000 }; in translate_attr_convert() local
710 imms[swizzle[0] - PIPE_SWIZZLE_0]); in translate_attr_convert()
720 imms[swizzle[1] - PIPE_SWIZZLE_0]); in translate_attr_convert()
738 imms[swizzle[2] - PIPE_SWIZZLE_0]); in translate_attr_convert()
748 imms[swizzle[3] - PIPE_SWIZZLE_0]); in translate_attr_convert()
770 unsigned imms[2] = { 0, 1 }; in translate_attr_convert() local
826 imms[1] = in translate_attr_convert()
854 imms[swizzle[1] - PIPE_SWIZZLE_0]); in translate_attr_convert()
861 (imms[swizzle[1] - PIPE_SWIZZLE_0] << 16) | in translate_attr_convert()
862 imms[swizzl in translate_attr_convert()
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/third_party/mesa3d/src/nouveau/codegen/
H A Dnv50_ir_build_util.cpp49 memset(imms, 0, sizeof(imms)); in init()
61 while (imms[pos]) in addImmediate()
63 imms[pos] = imm; in addImmediate()
375 while (imms[pos] && imms[pos]->reg.data.u32 != u) in mkImm()
378 ImmediateValue *imm = imms[pos]; in mkImm()
H A Dnv50_ir_build_util.h198 ImmediateValue *imms[NV50_IR_BUILD_IMM_HT_SIZE]; member in nv50_ir::BuildUtil
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h212 /// the form N:immr:imms.
291 /// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
294 // Extract the N, imms, and immr fields. in decodeLogicalImmediate()
297 unsigned imms = val & 0x3f; in decodeLogicalImmediate() local
300 int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f)); in decodeLogicalImmediate()
304 unsigned S = imms & (size - 1); in decodeLogicalImmediate()
319 /// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
323 // Extract the N and imms field in isValidDecodeLogicalImmediate()
325 unsigned imms = val & 0x3f; isValidDecodeLogicalImmediate() local
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H A DAArch64InstPrinter.cpp122 int64_t imms = Op3.getImm(); in printInst() local
123 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { in printInst()
125 shift = 31 - imms; in printInst()
126 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f && in printInst()
127 ((imms + 1 == immr))) { in printInst()
129 shift = 63 - imms; in printInst()
130 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) { in printInst()
133 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) { in printInst()
136 } else if (Opcode == AArch64::SBFMWri && imms in printInst()
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/third_party/node/deps/v8/src/codegen/arm64/
H A Dassembler-arm64-inl.h915 Instr Assembler::ImmS(unsigned imms, unsigned reg_size) { in ImmS() argument
916 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(imms)) || in ImmS()
917 ((reg_size == kWRegSizeInBits) && is_uint5(imms))); in ImmS()
919 return imms << ImmS_offset; in ImmS()
930 Instr Assembler::ImmSetBits(unsigned imms, unsigned reg_size) { in ImmSetBits() argument
932 DCHECK(is_uint6(imms)); in ImmSetBits()
933 DCHECK((reg_size == kXRegSizeInBits) || is_uint6(imms + 3)); in ImmSetBits()
935 return imms << ImmSetBits_offset; in ImmSetBits()
H A Dassembler-arm64.h593 void bfm(const Register& rd, const Register& rn, int immr, int imms);
596 void sbfm(const Register& rd, const Register& rn, int immr, int imms);
599 void ubfm(const Register& rd, const Register& rn, int immr, int imms);
2177 inline static Instr ImmS(unsigned imms, unsigned reg_size);
2179 inline static Instr ImmSetBits(unsigned imms, unsigned reg_size);
H A Dassembler-arm64.cc983 int imms) { in bfm()
987 ImmS(imms, rn.SizeInBits()) | Rn(rn) | Rd(rd)); in bfm()
991 int imms) { in sbfm()
995 ImmS(imms, rn.SizeInBits()) | Rn(rn) | Rd(rd)); in sbfm()
999 int imms) { in ubfm()
1003 ImmS(imms, rn.SizeInBits()) | Rn(rn) | Rd(rd)); in ubfm()
4047 // N imms immr size S R in IsImmLogical()
4215 // imms size S in IsImmLogical()
4223 // So we 'or' (-d * 2) with our computed s to form imms. in IsImmLogical()
982 bfm(const Register& rd, const Register& rn, int immr, int imms) bfm() argument
990 sbfm(const Register& rd, const Register& rn, int immr, int imms) sbfm() argument
998 ubfm(const Register& rd, const Register& rn, int immr, int imms) ubfm() argument
/third_party/node/deps/v8/src/compiler/backend/x64/
H A Dinstruction-selector-x64.cc3625 uint32_t imms[kMaxImms]; in VisitI8x16Shuffle() local
3651 imms[imm_count++] = shuffle_mask; in VisitI8x16Shuffle()
3661 imms[imm_count++] = offset; in VisitI8x16Shuffle()
3688 imms[imm_count++] = shuffle_mask; in VisitI8x16Shuffle()
3696 imms[imm_count++] = blend_mask; in VisitI8x16Shuffle()
3701 imms[imm_count++] = mask; in VisitI8x16Shuffle()
3712 imms[imm_count++] = shuffle_mask; in VisitI8x16Shuffle()
3714 imms[imm_count++] = blend_mask; in VisitI8x16Shuffle()
3722 imms[imm_count++] = blend_mask; in VisitI8x16Shuffle()
3727 imms[imm_coun in VisitI8x16Shuffle()
3800 auto imms = m.ResolvedValue().immediate(); VisitI8x16Swizzle() local
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H A Dcode-generator-x64.cc1102 void SetupSimdImmediateInRegister(TurboAssembler* assembler, uint32_t* imms, in SetupSimdImmediateInRegister() argument
1104 assembler->Move(reg, make_uint64(imms[3], imms[2]), in SetupSimdImmediateInRegister()
1105 make_uint64(imms[1], imms[0])); in SetupSimdImmediateInRegister()
/third_party/node/deps/v8/src/compiler/backend/ia32/
H A Dinstruction-selector-ia32.cc2879 uint32_t imms[kMaxImms]; in VisitI8x16Shuffle() local
2906 imms[imm_count++] = shuffle_mask; in VisitI8x16Shuffle()
2914 imms[imm_count++] = offset; in VisitI8x16Shuffle()
2940 imms[imm_count++] = shuffle_mask; in VisitI8x16Shuffle()
2948 imms[imm_count++] = blend_mask; in VisitI8x16Shuffle()
2957 imms[imm_count++] = shuffle_mask; in VisitI8x16Shuffle()
2959 imms[imm_count++] = blend_mask; in VisitI8x16Shuffle()
2967 imms[imm_count++] = blend_mask; in VisitI8x16Shuffle()
2971 imms[imm_count++] = index; in VisitI8x16Shuffle()
2979 imms[imm_coun in VisitI8x16Shuffle()
3036 auto imms = m.ResolvedValue().immediate(); VisitI8x16Swizzle() local
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/third_party/mesa3d/src/panfrost/bifrost/valhall/
H A Dvalhall.py300 imms = [build_imm(imm) for imm in el.findall('imm')]
309 instr = Instruction(name, opcode, opcode2, srcs = sources, dests = dests, immediates = imms, modifiers = modifiers, staging = staging, unit = unit)
/third_party/node/deps/v8/src/wasm/baseline/arm64/
H A Dliftoff-assembler-arm64.h2543 int64_t imms[2] = {0, 0}; in emit_i8x16_shuffle() local
2545 imms[0] = (imms[0] << 8) | (shuffle[i]); in emit_i8x16_shuffle()
2546 imms[1] = (imms[1] << 8) | (shuffle[i + 8]); in emit_i8x16_shuffle()
2548 DCHECK_EQ(0, (imms[0] | imms[1]) & in emit_i8x16_shuffle()
2551 Movi(temp.V16B(), imms[1], imms[0]); in emit_i8x16_shuffle()
2879 const uint8_t imms[1 in emit_i8x16_bitmask()
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/third_party/vixl/src/aarch64/
H A Dassembler-aarch64.h766 unsigned imms);
772 unsigned imms);
778 unsigned imms);
7288 static Instr SVEImmSetBits(unsigned imms, unsigned lane_size) {
7289 VIXL_ASSERT(IsUint6(imms));
7290 VIXL_ASSERT((lane_size == kDRegSize) || IsUint6(imms + 3));
7292 return imms << SVEImmSetBits_offset;
7337 static Instr ImmS(unsigned imms, unsigned reg_size) {
7338 VIXL_ASSERT(((reg_size == kXRegSize) && IsUint6(imms)) ||
7339 ((reg_size == kWRegSize) && IsUint5(imms)));
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H A Dassembler-aarch64.cc683 unsigned imms) { in bfm()
687 ImmS(imms, rn.GetSizeInBits()) | Rn(rn) | Rd(rd)); in bfm()
694 unsigned imms) { in sbfm()
698 ImmS(imms, rn.GetSizeInBits()) | Rn(rn) | Rd(rd)); in sbfm()
705 unsigned imms) { in ubfm()
709 ImmS(imms, rn.GetSizeInBits()) | Rn(rn) | Rd(rd)); in ubfm()
6528 // N imms immr size S R
6698 // imms size S
6706 // So we 'or' (2 * -d) with our computed s to form imms.
680 bfm(const Register& rd, const Register& rn, unsigned immr, unsigned imms) bfm() argument
691 sbfm(const Register& rd, const Register& rn, unsigned immr, unsigned imms) sbfm() argument
702 ubfm(const Register& rd, const Register& rn, unsigned immr, unsigned imms) ubfm() argument
H A Dmacro-assembler-aarch64.h1179 unsigned imms) { in Bfm()
1184 bfm(rd, rn, immr, imms); in Bfm()
2414 unsigned imms) { in Sbfm()
2419 sbfm(rd, rn, immr, imms); in Sbfm()
2706 unsigned imms) { in Ubfm()
2711 ubfm(rd, rn, immr, imms); in Ubfm()
1176 Bfm(const Register& rd, const Register& rn, unsigned immr, unsigned imms) Bfm() argument
2411 Sbfm(const Register& rd, const Register& rn, unsigned immr, unsigned imms) Sbfm() argument
2703 Ubfm(const Register& rd, const Register& rn, unsigned immr, unsigned imms) Ubfm() argument
/third_party/mesa3d/src/gallium/frontends/d3d10umd/
H A DShaderTGSI.c213 struct ureg_src imms; member
1025 reg = sx->imms; in translate_src_operand()
1030 reg = sx->imms; in translate_src_operand()
1033 sx->imms, in translate_src_operand()
1425 sx.imms = in Shader_tgsi_translate()
/third_party/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_tgsi_soa.c2994 LLVMValueRef imms[4]; in lp_emit_immediate_soa() local
3001 imms[i] = in lp_emit_immediate_soa()
3011 imms[i] = LLVMConstBitCast(tmp, bld_base->base.vec_type); in lp_emit_immediate_soa()
3018 imms[i] = LLVMConstBitCast(tmp, bld_base->base.vec_type); in lp_emit_immediate_soa()
3024 imms[i] = bld_base->base.undef; in lp_emit_immediate_soa()
3038 LLVMBuildStore(builder, imms[i], imm_ptr); in lp_emit_immediate_soa()
3047 bld->immediates[bld->num_immediates][i] = imms[i]; in lp_emit_immediate_soa()
/third_party/node/deps/v8/src/wasm/baseline/x64/
H A Dliftoff-assembler-x64.h2474 uint32_t imms[4]; in emit_i8x16_shuffle() local
2476 wasm::SimdShuffle::Pack16Lanes(imms, shuffle); in emit_i8x16_shuffle()
2477 TurboAssembler::Move(kScratchDoubleReg, make_uint64(imms[3], imms[2]), in emit_i8x16_shuffle()
2478 make_uint64(imms[1], imms[0])); in emit_i8x16_shuffle()
2840 const uint8_t imms[16]) { in emit_s128_const()
2842 memcpy(vals, imms, sizeof(vals)); in emit_s128_const()
2839 emit_s128_const(LiftoffRegister dst, const uint8_t imms[16]) emit_s128_const() argument
/third_party/node/deps/v8/src/wasm/baseline/ia32/
H A Dliftoff-assembler-ia32.h2865 uint32_t imms[4]; in emit_i8x16_shuffle() local
2867 wasm::SimdShuffle::Pack16Lanes(imms, shuffle); in emit_i8x16_shuffle()
2869 push_imm32(imms[i]); in emit_i8x16_shuffle()
3244 const uint8_t imms[16]) { in emit_s128_const()
3246 memcpy(vals, imms, sizeof(vals)); in emit_s128_const()
3243 emit_s128_const(LiftoffRegister dst, const uint8_t imms[16]) emit_s128_const() argument
/third_party/node/deps/v8/src/compiler/backend/arm64/
H A Dinstruction-selector-arm64.cc3950 auto imms = m.ResolvedValue().immediate(); in isSimdZero() local
3951 return (std::all_of(imms.begin(), imms.end(), std::logical_not<uint8_t>())); in isSimdZero()
/third_party/node/deps/v8/src/codegen/riscv64/
H A Dmacro-assembler-riscv64.h980 void WasmRvvS128const(VRegister dst, const uint8_t imms[16]);
/third_party/node/deps/v8/src/wasm/baseline/s390/
H A Dliftoff-assembler-s390.h2821 const uint8_t imms[16]) { in emit_s128_const()
2823 memcpy(vals, imms, sizeof(vals)); in emit_s128_const()
2820 emit_s128_const(LiftoffRegister dst, const uint8_t imms[16]) emit_s128_const() argument

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