| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64-inl.h | 996 Instr Assembler::ImmLSPair(int imm7, unsigned size) { in ImmLSPair() argument
997 DCHECK_EQ(imm7, in ImmLSPair()
998 static_cast<int>(static_cast<uint32_t>(imm7 >> size) << size)); in ImmLSPair()
999 int scaled_imm7 = imm7 >> size; in ImmLSPair()
1019 Instr Assembler::ImmHint(int imm7) { in ImmHint() argument
1020 DCHECK(is_uint7(imm7)); in ImmHint()
1021 return imm7 << ImmHint_offset; in ImmHint()
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| H A D | assembler-arm64.h | 2197 inline static Instr ImmLSPair(int imm7, unsigned size);
2201 inline static Instr ImmHint(int imm7);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 636 unsigned imm7 = 0; in DecodeTRAP() local
638 imm7 = fieldFromInstruction(insn, 0, 7); in DecodeTRAP()
649 MI.addOperand(MCOperand::createImm(imm7)); in DecodeTRAP()
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| /third_party/vixl/src/aarch64/ |
| H A D | assembler-aarch64.h | 2196 void hint(int imm7);
3903 unsigned imm7);
3915 unsigned imm7);
3939 unsigned imm7);
3951 unsigned imm7);
7417 static Instr ImmLSPair(int64_t imm7, unsigned access_size_in_bytes_log2) {
7419 VIXL_ASSERT(IsMultiple(imm7, access_size_in_bytes));
7420 int64_t scaled_imm7 = imm7 / access_size_in_bytes;
7464 static Instr ImmHint(int imm7) {
7465 VIXL_ASSERT(IsUint7(imm7));
[all...] |
| H A D | assembler-sve-aarch64.cc | 2907 unsigned imm7) { in cmphi()
2910 // size<23:22> | imm7<20:14> | lt<13> = 0 | Pg<12:10> | Zn<9:5> | ne<4> = 1 | in cmphi()
2916 CompareVectors(pd, pg, zn, imm7, CMPHI_p_p_zi); in cmphi()
2922 unsigned imm7) { in cmphs()
2925 // size<23:22> | imm7<20:14> | lt<13> = 0 | Pg<12:10> | Zn<9:5> | ne<4> = 0 | in cmphs()
2931 CompareVectors(pd, pg, zn, imm7, CMPHS_p_p_zi); in cmphs()
2937 unsigned imm7) { in cmplo()
2940 // size<23:22> | imm7<20:14> | lt<13> = 1 | Pg<12:10> | Zn<9:5> | ne<4> = 0 | in cmplo()
2946 CompareVectors(pd, pg, zn, imm7, CMPLO_p_p_zi); in cmplo()
2952 unsigned imm7) { in cmpls()
2904 cmphi(const PRegisterWithLaneSize& pd, const PRegisterZ& pg, const ZRegister& zn, unsigned imm7) cmphi() argument
2919 cmphs(const PRegisterWithLaneSize& pd, const PRegisterZ& pg, const ZRegister& zn, unsigned imm7) cmphs() argument
2934 cmplo(const PRegisterWithLaneSize& pd, const PRegisterZ& pg, const ZRegister& zn, unsigned imm7) cmplo() argument
2949 cmpls(const PRegisterWithLaneSize& pd, const PRegisterZ& pg, const ZRegister& zn, unsigned imm7) cmpls() argument
[all...] |
| H A D | assembler-aarch64.cc | 1937 void Assembler::hint(int imm7) { in hint() argument
1938 VIXL_ASSERT(IsUint7(imm7)); in hint()
1939 Emit(HINT | ImmHint(imm7) | Rt(xzr)); in hint()
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| H A D | macro-assembler-aarch64.h | 1750 void Hint(int imm7) { in Hint() argument
1753 hint(imm7); in Hint()
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| /third_party/node/deps/v8/src/execution/arm/ |
| H A D | simulator-arm.cc | 5550 int imm7 = instr->Bits(21, 16); in DecodeAdvancedSIMDDataProcessing() local
5551 imm7 += (l << 6); in DecodeAdvancedSIMDDataProcessing()
5552 int size = base::bits::RoundDownToPowerOfTwo32(imm7); in DecodeAdvancedSIMDDataProcessing()
5558 int shift = 2 * size - imm7; in DecodeAdvancedSIMDDataProcessing()
5582 int shift = 2 * size - imm7; in DecodeAdvancedSIMDDataProcessing()
5660 int shift = imm7 - size; in DecodeAdvancedSIMDDataProcessing()
5681 int shift = 2 * size - imm7; in DecodeAdvancedSIMDDataProcessing()
5702 int shift = imm7 - size; in DecodeAdvancedSIMDDataProcessing()
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| /third_party/node/deps/v8/src/codegen/riscv64/ |
| H A D | constants-riscv64.h | 1777 int32_t imm7 =
1779 return imm7;
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| /third_party/vixl/test/aarch64/ |
| H A D | test-disasm-aarch64.cc | 3184 COMPARE(stgp(x301, x302, x30, int imm7), "stgp <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]"); in TEST()
3185 COMPARE(stgp(x201, x202, x20, int imm7), "stgp <Xt1>, <Xt2>, [<Xn|SP>], #<imm>"); in TEST()
3186 COMPARE(stgp(x161, x162, x16, int imm7), "stgp <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!"); in TEST()
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