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Searched refs:imm2 (Results 1 - 18 of 18) sorted by relevance

/third_party/mesa3d/src/panfrost/bifrost/valhall/test/
H A Dtest-validate-fau.cpp50 imm2 = bi_fau((enum bir_fau) (BIR_FAU_IMMEDIATE | 2), false); in ValidateFau()
64 bi_index zero, imm1, imm2, unif, unif_hi, unif2, core_id, lane_id; member in ValidateFau
90 INVALID(bi_fma_f32_to(b, bi_register(1), zero, imm1, imm2)); in TEST_F()
/third_party/pcre2/pcre2/src/sljit/
H A DsljitNativeARM_T2_32.c602 sljit_uw imm, imm2; in emit_op_imm() local
632 imm2 = NEGATE(imm); in emit_op_imm()
636 if (imm2 <= 0x7) in emit_op_imm()
637 return push_inst16(compiler, SUBSI3 | IMM3(imm2) | RD3(dst) | RN3(reg)); in emit_op_imm()
641 if (imm2 <= 0xff) in emit_op_imm()
642 return push_inst16(compiler, SUBSI8 | IMM8(imm2) | RDN3(dst)); in emit_op_imm()
648 if (imm2 <= 0xfff) in emit_op_imm()
649 return push_inst32(compiler, SUBWI | RD4(dst) | RN4(reg) | IMM12(imm2)); in emit_op_imm()
651 imm2 = get_imm(imm); in emit_op_imm()
652 if (imm2 ! in emit_op_imm()
1368 sljit_uw imm2; emit_add_sp() local
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H A DsljitNativeARM_32.c1246 sljit_uw imm2 = get_imm(imm); in emit_add_sp() local
1248 if (imm2 == 0) { in emit_add_sp()
1249 imm2 = (imm & ~(sljit_uw)0x3ff) >> 10; in emit_add_sp()
1252 FAIL_IF(push_inst(compiler, ADD | SRC2_IMM | RD(SLJIT_SP) | RN(SLJIT_SP) | 0xb00 | imm2)); in emit_add_sp()
1256 return push_inst(compiler, ADD | RD(SLJIT_SP) | RN(SLJIT_SP) | imm2); in emit_add_sp()
1663 sljit_uw imm2; in generate_int() local
1706 imm2 = SRC2_IMM | ((imm >> 8) & 0xff) | (((rol + 8) & 0xf) << 8); in generate_int()
1729 imm2 = SRC2_IMM | (imm >> 24) | ((rol & 0xf) << 8); in generate_int()
1759 imm2 = SRC2_IMM | (imm >> 24) | ((rol & 0xf) << 8); in generate_int()
1765 FAIL_IF(push_inst(compiler, (positive ? ORR : BIC) | RD(reg) | RN(reg) | imm2)); in generate_int()
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/third_party/node/deps/v8/src/codegen/arm64/
H A Dassembler-arm64-inl.h1024 Instr Assembler::ImmBarrierDomain(int imm2) { in ImmBarrierDomain() argument
1025 DCHECK(is_uint2(imm2)); in ImmBarrierDomain()
1026 return imm2 << ImmBarrierDomain_offset; in ImmBarrierDomain()
1029 Instr Assembler::ImmBarrierType(int imm2) { in ImmBarrierType() argument
1030 DCHECK(is_uint2(imm2)); in ImmBarrierType()
1031 return imm2 << ImmBarrierType_offset; in ImmBarrierType()
H A Dassembler-arm64.h2202 inline static Instr ImmBarrierDomain(int imm2);
2203 inline static Instr ImmBarrierType(int imm2);
/third_party/node/deps/v8/src/wasm/
H A Dwasm-module-builder.h187 void EmitWithU8U8(WasmOpcode opcode, const byte imm1, const byte imm2);
H A Dwasm-module-builder.cc114 const byte imm2) { in EmitWithU8U8()
117 body_.write_u8(imm2); in EmitWithU8U8()
113 EmitWithU8U8(WasmOpcode opcode, const byte imm1, const byte imm2) EmitWithU8U8() argument
/third_party/mesa3d/src/nouveau/codegen/
H A Dnv50_ir_peephole.cpp791 ImmediateValue &imm2) in expr()
793 struct Storage *const a = &imm0.reg, *const b = &imm1.reg, *const c = &imm2.reg; in expr()
907 const int s, ImmediateValue& imm2) in tryCollapseChainedMULs()
913 float f = imm2.reg.data.f32 * exp2f(mul2->postFactor); in tryCollapseChainedMULs()
929 // d = mul a, imm2 -> d = mul r, (imm1 * imm2) in tryCollapseChainedMULs()
971 ConstantFolding::opnd3(Instruction *i, ImmediateValue &imm2) in opnd3() argument
976 if (imm2.isInteger(0)) { in opnd3()
984 if (imm2.isInteger(0)) { in opnd3()
788 expr(Instruction *i, ImmediateValue &imm0, ImmediateValue &imm1, ImmediateValue &imm2) expr() argument
906 tryCollapseChainedMULs(Instruction *mul2, const int s, ImmediateValue& imm2) tryCollapseChainedMULs() argument
/third_party/vixl/test/aarch64/
H A Dtest-simulator-aarch64.cc217 const VRegister& vd, int imm1, const VRegister& vn, int imm2);
2788 for (unsigned imm2 = 0; imm2 < inputs_imm2_length; imm2++) { in TestOpImmOpImmNEON()
2797 (imm2 * vd_lane_count) + lane; in TestOpImmOpImmNEON()
2824 (imm2 * vd_lane_count) + lane; in TestOpImmOpImmNEON()
2829 unsigned input_index_imm2 = imm2; in TestOpImmOpImmNEON()
/third_party/vixl/src/aarch64/
H A Dassembler-aarch64.h7494 static Instr ImmBarrierDomain(int imm2) {
7495 VIXL_ASSERT(IsUint2(imm2));
7496 return imm2 << ImmBarrierDomain_offset;
7499 static Instr ImmBarrierType(int imm2) {
7500 VIXL_ASSERT(IsUint2(imm2));
7501 return imm2 << ImmBarrierType_offset;
H A Ddisasm-aarch64.cc4044 int imm2 = instr->ExtractBits(23, 22); in Disassembler() local
4045 if ((CountSetBits(imm2) + CountSetBits(tsz)) == 1) { in Disassembler()
4046 // If imm2:tsz has one set bit, the index is zero. This is in Disassembler()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1571 MCOperand imm2(MCOperand::createExpr(Expr)); // lower 32 in processInstruction()
1572 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2); in processInstruction()
/third_party/node/deps/v8/src/compiler/backend/arm/
H A Dcode-generator-arm.cc2845 uint64_t imm2 = make_uint64(i.InputUint32(3), i.InputUint32(2)); in AssembleArchInstruction()
2847 __ vmov(dst.high(), base::Double(imm2)); in AssembleArchInstruction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp238 uint64_t imm2, unsigned Op3, bool Op3IsKill) { in fastEmitInst_riir()
236 fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t imm1, uint64_t imm2, unsigned Op3, bool Op3IsKill) fastEmitInst_riir() argument
/third_party/node/deps/v8/src/compiler/backend/mips64/
H A Dcode-generator-mips64.cc2046 uint64_t imm2 = make_uint64(i.InputUint32(3), i.InputUint32(2)); in AssembleArchInstruction() local
2049 __ li(kScratchReg, imm2); in AssembleArchInstruction()
/third_party/node/deps/v8/src/compiler/backend/riscv64/
H A Dcode-generator-riscv64.cc2758 int64_t imm2 = make_uint64(i.InputInt32(5), i.InputInt32(4)); in AssembleArchInstruction() local
2760 __ li(kScratchReg, imm2); in AssembleArchInstruction()
/third_party/node/deps/v8/src/codegen/riscv64/
H A Dmacro-assembler-riscv64.cc3979 uint64_t imm2 = *((reinterpret_cast<const uint64_t*>(imms)) + 1); in WasmRvvS128const() local
3985 li(kScratchReg, imm2); in WasmRvvS128const()
/third_party/node/deps/v8/src/wasm/baseline/riscv64/
H A Dliftoff-assembler-riscv64.h1886 uint64_t imm2 = *((reinterpret_cast<const uint64_t*>(shuffle)) + 1); in emit_i8x16_shuffle() local
1888 li(kScratchReg, imm2); in emit_i8x16_shuffle()

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