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Searched refs:hw_res (Results 1 - 16 of 16) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/virgl/
H A Dvirgl_staging_mgr.c42 vws->resource_reference(vws, &staging->hw_res, NULL); in virgl_staging_alloc_buffer()
48 staging->hw_res = vws->resource_create(vws, in virgl_staging_alloc_buffer()
61 if (staging->hw_res == NULL) in virgl_staging_alloc_buffer()
64 staging->map = vws->resource_map(vws, staging->hw_res); in virgl_staging_alloc_buffer()
66 vws->resource_reference(vws, &staging->hw_res, NULL); in virgl_staging_alloc_buffer()
90 vws->resource_reference(vws, &staging->hw_res, NULL); in virgl_staging_destroy()
124 assert(staging->hw_res); in virgl_staging_alloc()
131 vws->resource_reference(vws, outbuf, staging->hw_res); in virgl_staging_alloc()
H A Dvirgl_resource.c124 if (!vws->res_is_referenced(vws, vctx->cbuf, res->hw_res)) in virgl_res_needs_flush()
226 wait = (flush || vws->resource_is_busy(vws, res->hw_res)); in virgl_resource_transfer_prepare()
275 (readback || (wait && vws->resource_is_busy(vws, res->hw_res)))) in virgl_resource_transfer_prepare()
283 vws->resource_wait(vws, res->hw_res); in virgl_resource_transfer_prepare()
284 vws->transfer_get(vws, res->hw_res, &xfer->base.box, xfer->base.stride, in virgl_resource_transfer_prepare()
292 vws->resource_wait(vws, res->hw_res); in virgl_resource_transfer_prepare()
441 struct virgl_hw_res *hw_res; in virgl_resource_realloc() local
448 hw_res = vs->vws->resource_create(vs->vws, in virgl_resource_realloc()
461 if (!hw_res) in virgl_resource_realloc()
464 vs->vws->resource_reference(vs->vws, &res->hw_res, NUL in virgl_resource_realloc()
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H A Dvirgl_transfer_queue.c106 const struct virgl_hw_res *hw_res, in transfer_overlap()
113 if (xfer->hw_res != hw_res || xfer->base.level != level) in transfer_overlap()
141 const struct virgl_hw_res *hw_res, in virgl_transfer_queue_find_overlap()
148 if (transfer_overlap(xfer, hw_res, level, box, include_touching)) in virgl_transfer_queue_find_overlap()
158 return transfer_overlap(queued, current->hw_res, current->base.level, in transfers_intersect()
187 queue->vs->vws->transfer_put(queue->vs->vws, queued->hw_res, in transfer_put()
352 transfer->hw_res, in virgl_transfer_queue_is_queued()
360 const struct virgl_hw_res *hw_res, in virgl_transfer_queue_extend_buffer()
368 queued = virgl_transfer_queue_find_overlap(queue, hw_res, in virgl_transfer_queue_extend_buffer()
105 transfer_overlap(const struct virgl_transfer *xfer, const struct virgl_hw_res *hw_res, unsigned level, const struct pipe_box *box, bool include_touching) transfer_overlap() argument
140 virgl_transfer_queue_find_overlap(const struct virgl_transfer_queue *queue, const struct virgl_hw_res *hw_res, unsigned level, const struct pipe_box *box, bool include_touching) virgl_transfer_queue_find_overlap() argument
359 virgl_transfer_queue_extend_buffer(struct virgl_transfer_queue *queue, const struct virgl_hw_res *hw_res, unsigned offset, unsigned size, const void *data) virgl_transfer_queue_extend_buffer() argument
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H A Dvirgl_query.c158 host_state = vs->vws->resource_map(vs->vws, query->buf->hw_res); in virgl_end_query()
169 vs->vws->emit_res(vs->vws, vctx->cbuf, query->buf->hw_res, false); in virgl_end_query()
187 if (vs->vws->res_is_referenced(vs->vws, vctx->cbuf, query->buf->hw_res)) in virgl_get_query_result()
191 vs->vws->resource_wait(vs->vws, query->buf->hw_res); in virgl_get_query_result()
192 else if (vs->vws->resource_is_busy(vs->vws, query->buf->hw_res)) in virgl_get_query_result()
195 host_state = vs->vws->resource_map(vs->vws, query->buf->hw_res); in virgl_get_query_result()
H A Dvirgl_resource.h55 struct virgl_hw_res *hw_res; member
83 struct virgl_hw_res *hw_res; member
H A Dvirgl_staging_mgr.h41 struct virgl_hw_res *hw_res; /* Staging buffer hw_res. */ member
H A Dvirgl_transfer_queue.h62 const struct virgl_hw_res *hw_res,
H A Dvirgl_context.c183 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE); in virgl_attach_res_framebuffer()
192 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE); in virgl_attach_res_framebuffer()
209 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE); in virgl_attach_res_sampler_views()
223 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE); in virgl_attach_res_vertex_buffers()
235 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE); in virgl_attach_res_index_buffer()
247 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE); in virgl_attach_res_so_targets()
264 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE); in virgl_attach_res_uniform_buffers()
281 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE); in virgl_attach_res_shader_buffers()
298 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE); in virgl_attach_res_shader_images()
312 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALS in virgl_attach_res_atomic_buffers()
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H A Dvirgl_texture.c184 ptr = vws->resource_map(vws, vtex->hw_res); in texture_transfer_map_resolve()
252 vws->transfer_put(vws, trans->hw_res, box, in flush_data()
H A Dvirgl_streamout.c86 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE); in virgl_set_so_targets()
H A Dvirgl_encode.c328 if (res && res->hw_res) in virgl_encoder_emit_resource()
329 vws->emit_res(vws, buf, res->hw_res, TRUE); in virgl_encoder_emit_resource()
882 * this transfer targets, which is saved in xfer->hw_res. in virgl_encoder_transfer3d_common()
884 vs->vws->emit_res(vs->vws, buf, xfer->hw_res, TRUE); in virgl_encoder_transfer3d_common()
910 transfer.hw_res = res->hw_res; in virgl_encoder_inline_write()
H A Dvirgl_screen.c824 vws->flush_frontbuffer(vws, vres->hw_res, level, layer, winsys_drawable_handle, in virgl_flush_frontbuffer()
925 vscreen->vws->resource_wait(vscreen->vws, res->hw_res); in virgl_query_memory_info()
/third_party/mesa3d/src/gallium/drivers/virgl/tests/
H A Dvirgl_staging_mgr_test.cpp53 struct virgl_hw_res *hw_res = CALLOC_STRUCT(virgl_hw_res); in fake_resource_create() local
55 pipe_reference_init(&hw_res->reference, 1); in fake_resource_create()
57 hw_res->target = target; in fake_resource_create()
58 hw_res->bind = bind; in fake_resource_create()
59 hw_res->size = size; in fake_resource_create()
60 hw_res->data = CALLOC(size, 1); in fake_resource_create()
62 return hw_res; in fake_resource_create()
81 fake_resource_map(struct virgl_winsys *vws, struct virgl_hw_res *hw_res) in fake_resource_map() argument
83 return hw_res->data; in fake_resource_map()
115 resource_map(struct virgl_hw_res *hw_res) in resource_map() argument
350 failing_resource_map(struct virgl_winsys *vws, struct virgl_hw_res *hw_res) failing_resource_map() argument
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/third_party/mesa3d/src/gallium/winsys/virgl/drm/
H A Dvirgl_drm_winsys.h108 struct virgl_hw_res *hw_res; member
H A Dvirgl_drm_winsys.c924 fence->hw_res = virgl_drm_winsys_resource_create(vws, PIPE_BUFFER, in virgl_drm_fence_create_legacy()
926 if (!fence->hw_res) { in virgl_drm_fence_create_legacy()
1055 return !virgl_drm_resource_is_busy(vws, fence->hw_res); in virgl_fence_wait()
1060 while (virgl_drm_resource_is_busy(vws, fence->hw_res)) { in virgl_fence_wait()
1067 virgl_drm_resource_wait(vws, fence->hw_res); in virgl_fence_wait()
1083 virgl_drm_resource_reference(vws, &dfence->hw_res, NULL); in virgl_fence_reference()
/third_party/backends/backend/
H A Davision.c2957 const int* hw_res; in compute_parameters() local
2961 for (hw_res = hw_res_list; *hw_res && *hw_res < s->avdimen.xres; ++hw_res) in compute_parameters()
2963 s->avdimen.hw_xres = *hw_res; in compute_parameters()
2965 for (hw_res = hw_res_list; *hw_res && *hw_res < s->avdimen.yres; ++hw_res) in compute_parameters()
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