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Searched refs:gfx9 (Results 1 - 25 of 39) sorted by relevance

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/third_party/mesa3d/src/amd/common/
H A Dac_surface.c151 return (!surf->u.gfx9.color.dcc.independent_64B_blocks && in ac_surface_supports_dcc_image_stores()
152 surf->u.gfx9.color.dcc.independent_128B_blocks && in ac_surface_supports_dcc_image_stores()
153 surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_128B) || in ac_surface_supports_dcc_image_stores()
155 surf->u.gfx9.color.dcc.independent_64B_blocks && in ac_surface_supports_dcc_image_stores()
156 surf->u.gfx9.color.dcc.independent_128B_blocks && in ac_surface_supports_dcc_image_stores()
157 surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B); in ac_surface_supports_dcc_image_stores()
186 surf->u.gfx9.color.dcc.independent_64B_blocks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier); in ac_modifier_fill_dcc_params()
187 surf->u.gfx9.color.dcc.independent_128B_blocks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier); in ac_modifier_fill_dcc_params()
188 surf->u.gfx9.color.dcc.max_compressed_block_size = AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier); in ac_modifier_fill_dcc_params()
1527 return surf->u.gfx9 in is_dcc_supported_by_L2()
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H A Dac_surface_modifier_test.c78 din.swizzleMode = surf->u.gfx9.swizzle_mode; in get_addr_from_coord_base()
86 din.dccKeyFlags.pipeAligned = surf->u.gfx9.color.dcc.pipe_aligned; in get_addr_from_coord_base()
87 din.dccKeyFlags.rbAligned = surf->u.gfx9.color.dcc.rb_aligned; in get_addr_from_coord_base()
95 dcc_input.swizzleMode = surf->u.gfx9.swizzle_mode; in get_addr_from_coord_base()
128 _mesa_sha1_update(&ctx, &surf->u.gfx9.color.display_dcc_pitch_max, in generate_hash()
129 sizeof(surf->u.gfx9.color.display_dcc_pitch_max)); in generate_hash()
133 input.swizzleMode = surf->u.gfx9.swizzle_mode; in generate_hash()
142 input.pitchInElement = surf->u.gfx9.surf_pitch; in generate_hash()
148 surf->u.gfx9.color.dcc.rb_aligned, in generate_hash()
149 surf->u.gfx9 in generate_hash()
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H A Dac_surface_meta_address_test.c266 assert(dout.equation.gfx9.num_bits <= ARRAY_SIZE(eq.u.gfx9.bit)); in one_dcc_address_test()
288 addr = gfx9_meta_addr_from_coord(info, &dout.equation.gfx9, dout.metaBlkWidth, dout.metaBlkHeight, in one_dcc_address_test()
294 gfx9_meta_addr_from_coord(info, &dout.equation.gfx9, dout.metaBlkWidth, dout.metaBlkHeight, in one_dcc_address_test()
368 /* addrlib can do DccAddrFromCoord with MSAA images only on gfx9 */ in run_dcc_address_test()
642 addr = gfx9_meta_addr_from_coord(info, &cout.equation.gfx9, in one_cmask_address_test()
H A Dac_surface.h68 RADEON_MICRO_MODE_RENDER = 3, /* gfx9 and older: rotated */
84 /* Force a swizzle mode (gfx9+) or tile mode (gfx6-8).
182 * The gfx9 equation doesn't support mipmapping.
187 * The gfx9 equation isn't implemented.
196 /* The gfx9 DCC equation is chip-specific, and it varies with:
215 } gfx9; member
231 uint16_t epitch; /* gfx9 only, not on gfx10 */
262 uint16_t fmask_epitch; /* gfx9 only, not on gfx10 */
298 uint16_t stencil_epitch; /* gfx9 only, not on gfx10 */
394 struct gfx9_surf_layout gfx9; member
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/third_party/mesa3d/src/amd/compiler/
H A Daco_opcodes.py385 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOP2, InstrClass.Salu):
386 opcode(name, gfx7, gfx9, gfx10, Format.SOP2, cls)
421 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOPK, InstrClass.Salu):
422 opcode(name, gfx7, gfx9, gfx10, Format.SOPK, cls)
499 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOP1, InstrClass.Salu):
500 opcode(name, gfx7, gfx9, gfx10, Format.SOP1, cls)
527 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOPC:
528 opcode(name, gfx7, gfx9, gfx10, Format.SOPC, InstrClass.Salu)
574 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOPP, InstrClass.Salu):
575 opcode(name, gfx7, gfx9, gfx1
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/third_party/mesa3d/src/amd/vulkan/
H A Dradv_sdma_copy_image.c79 uint64_t src_address = image->bindings[0].bo->va + image->planes[0].surface.u.gfx9.surf_offset; in radv_sdma_v4_v5_copy_image_to_buffer()
80 unsigned src_pitch = image->planes[0].surface.u.gfx9.surf_pitch; in radv_sdma_v4_v5_copy_image_to_buffer()
98 src_address += image->planes[0].surface.u.gfx9.offset[0]; in radv_sdma_v4_v5_copy_image_to_buffer()
150 util_logbase2(bpp) | image->planes[0].surface.u.gfx9.swizzle_mode << 3 | in radv_sdma_v4_v5_copy_image_to_buffer()
151 image->planes[0].surface.u.gfx9.resource_type << 9 | in radv_sdma_v4_v5_copy_image_to_buffer()
152 (is_v5 ? 0 /* tiled->buffer.b.b.last_level */ : image->planes[0].surface.u.gfx9.epitch) in radv_sdma_v4_v5_copy_image_to_buffer()
174 image->planes[0].surface.u.gfx9.color.dcc.max_compressed_block_size << 24 | in radv_sdma_v4_v5_copy_image_to_buffer()
176 image->planes[0].surface.u.gfx9.color.dcc.pipe_aligned << 31); in radv_sdma_v4_v5_copy_image_to_buffer()
H A Dradv_meta_dcc_retile.c61 nir_imm_ivec2(&b, surf->u.gfx9.color.dcc_block_width, surf->u.gfx9.color.dcc_block_height)); in build_dcc_retile_compute_shader()
64 &surf->u.gfx9.color.dcc_equation, src_dcc_pitch, in build_dcc_retile_compute_shader()
68 &b, &dev->physical_device->rad_info, surf->bpe, &surf->u.gfx9.color.display_dcc_equation, in build_dcc_retile_compute_shader()
171 &vk_pipeline_info, NULL, &device->meta_state.dcc_retile.pipeline[surf->u.gfx9.swizzle_mode]); in radv_device_init_meta_dcc_retile_state()
195 unsigned swizzle_mode = image->planes[0].surface.u.gfx9.swizzle_mode; in radv_retile_dcc()
231 .range = image->planes[0].surface.u.gfx9.color.display_dcc_size, in radv_retile_dcc()
262 unsigned dcc_width = DIV_ROUND_UP(width, image->planes[0].surface.u.gfx9.color.dcc_block_width); in radv_retile_dcc()
264 DIV_ROUND_UP(height, image->planes[0].surface.u.gfx9.color.dcc_block_height); in radv_retile_dcc()
267 image->planes[0].surface.u.gfx9 in radv_retile_dcc()
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H A Dradv_image.c114 return info->bo_metadata->u.gfx9.scanout; in radv_surface_has_scanout()
427 if (md->u.gfx9.swizzle_mode > 0) in radv_patch_surface_from_metadata()
432 surface->u.gfx9.swizzle_mode = md->u.gfx9.swizzle_mode; in radv_patch_surface_from_metadata()
781 va += plane->surface.u.gfx9.zs.stencil_offset; in si_set_mutable_tex_desc_fields()
783 va += plane->surface.u.gfx9.surf_offset; in si_set_mutable_tex_desc_fields()
819 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.zs.stencil_swizzle_mode); in si_set_mutable_tex_desc_fields()
821 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.swizzle_mode); in si_set_mutable_tex_desc_fields()
833 meta = plane->surface.u.gfx9.color.dcc; in si_set_mutable_tex_desc_fields()
848 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9 in si_set_mutable_tex_desc_fields()
883 radv_tex_dim(VkImageType image_type, VkImageViewType view_type, unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9) radv_tex_dim() argument
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H A Dradv_device.c4845 offset = surface->u.gfx9.surf_slice_size * layer + surface->u.gfx9.prt_level_offset[level]; in radv_sparse_image_bind_memory()
4846 pitch = surface->u.gfx9.prt_level_pitch[level]; in radv_sparse_image_bind_memory()
6199 iview->image->planes[0].surface.u.gfx9.color.dcc.max_compressed_block_size; in radv_init_dcc_control_reg()
6200 independent_128b_blocks = iview->image->planes[0].surface.u.gfx9.color.dcc.independent_128B_blocks; in radv_init_dcc_control_reg()
6201 independent_64b_blocks = iview->image->planes[0].surface.u.gfx9.color.dcc.independent_64B_blocks; in radv_init_dcc_control_reg()
6267 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.swizzle_mode) | in radv_initialise_color_surface()
6268 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.color.dcc.pipe_aligned); in radv_initialise_color_surface()
6270 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.swizzle_mode) | in radv_initialise_color_surface()
6271 S_028EE0_FMASK_SW_MODE(surf->u.gfx9 in radv_initialise_color_surface()
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H A Dradv_meta_fmask_copy.c281 src_image->planes[0].surface.u.gfx9.color.fmask_swizzle_mode != in radv_can_use_fmask_copy()
282 dst_image->planes[0].surface.u.gfx9.color.fmask_swizzle_mode) in radv_can_use_fmask_copy()
H A Dradv_meta_clear.c1316 image->planes[0].surface.u.gfx9.meta_levels[level].offset; in radv_clear_dcc()
1317 size = image->planes[0].surface.u.gfx9.meta_levels[level].size * layer_count; in radv_clear_dcc()
1436 DIV_ROUND_UP(width, image->planes[0].surface.u.gfx9.color.dcc_block_width); in radv_clear_dcc_comp_to_single()
1438 DIV_ROUND_UP(height, image->planes[0].surface.u.gfx9.color.dcc_block_height); in radv_clear_dcc_comp_to_single()
1441 image->planes[0].surface.u.gfx9.color.dcc_block_width, in radv_clear_dcc_comp_to_single()
1442 image->planes[0].surface.u.gfx9.color.dcc_block_height, in radv_clear_dcc_comp_to_single()
1479 image->planes[0].surface.u.gfx9.meta_levels[level].offset; in radv_clear_htile()
1480 uint32_t size = image->planes[0].surface.u.gfx9.meta_levels[level].size; in radv_clear_htile()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_sdma_copy_image.c116 uint64_t dst_address = sdst->buffer.gpu_address + sdst->surface.u.gfx9.surf_offset; in si_sdma_v4_v5_copy_texture()
117 uint64_t src_address = ssrc->buffer.gpu_address + ssrc->surface.u.gfx9.surf_offset; in si_sdma_v4_v5_copy_texture()
118 unsigned dst_pitch = sdst->surface.u.gfx9.surf_pitch; in si_sdma_v4_v5_copy_texture()
119 unsigned src_pitch = ssrc->surface.u.gfx9.surf_pitch; in si_sdma_v4_v5_copy_texture()
135 src_address += ssrc->surface.u.gfx9.offset[0]; in si_sdma_v4_v5_copy_texture()
136 dst_address += sdst->surface.u.gfx9.offset[0]; in si_sdma_v4_v5_copy_texture()
159 unsigned linear_slice_pitch = ((uint64_t)linear->surface.u.gfx9.surf_slice_size) / bpp; in si_sdma_v4_v5_copy_texture()
167 linear_address += linear->surface.u.gfx9.offset[0]; in si_sdma_v4_v5_copy_texture()
189 tiled->surface.u.gfx9.swizzle_mode << 3 | in si_sdma_v4_v5_copy_texture()
190 tiled->surface.u.gfx9 in si_sdma_v4_v5_copy_texture()
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H A Dsi_shaderlib_nir.c166 coord = nir_imul(&b, coord, nir_imm_ivec2(&b, surf->u.gfx9.color.dcc_block_width, in si_create_dcc_retile_cs()
167 surf->u.gfx9.color.dcc_block_height)); in si_create_dcc_retile_cs()
170 ac_nir_dcc_addr_from_coord(&b, &sctx->screen->info, surf->bpe, &surf->u.gfx9.color.dcc_equation, in si_create_dcc_retile_cs()
178 ac_nir_dcc_addr_from_coord(&b, &sctx->screen->info, surf->bpe, &surf->u.gfx9.color.display_dcc_equation, in si_create_dcc_retile_cs()
212 nir_channels(&b, nir_imm_ivec4(&b, tex->surface.u.gfx9.color.dcc_block_width, in gfx9_create_clear_dcc_msaa_cs()
213 tex->surface.u.gfx9.color.dcc_block_height, in gfx9_create_clear_dcc_msaa_cs()
214 tex->surface.u.gfx9.color.dcc_block_depth, 0), 0x7)); in gfx9_create_clear_dcc_msaa_cs()
218 &tex->surface.u.gfx9.color.dcc_equation, in gfx9_create_clear_dcc_msaa_cs()
H A Dsi_compute_blit.c64 * This makes KHR-GL45.texture_view.view_classes pass on gfx9. in si_use_compute_copy_for_float_formats()
596 ((struct si_texture*)images[i].resource)->surface.u.gfx9.color.dcc.pipe_aligned); in si_launch_grid_internal_images()
791 sctx->cs_user_data[1] = (tex->surface.u.gfx9.color.dcc_pitch_max + 1) | in si_retile_dcc()
792 (tex->surface.u.gfx9.color.dcc_height << 16); in si_retile_dcc()
793 sctx->cs_user_data[2] = (tex->surface.u.gfx9.color.display_dcc_pitch_max + 1) | in si_retile_dcc()
794 (tex->surface.u.gfx9.color.display_dcc_height << 16); in si_retile_dcc()
799 void **shader = &sctx->cs_dcc_retile[tex->surface.u.gfx9.swizzle_mode]; in si_retile_dcc()
804 unsigned width = DIV_ROUND_UP(tex->buffer.b.b.width0, tex->surface.u.gfx9.color.dcc_block_width); in si_retile_dcc()
805 unsigned height = DIV_ROUND_UP(tex->buffer.b.b.height0, tex->surface.u.gfx9.color.dcc_block_height); in si_retile_dcc()
839 sctx->cs_user_data[0] = (tex->surface.u.gfx9 in gfx9_clear_dcc_msaa()
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H A Dsi_clear.c440 dcc_offset += tex->surface.u.gfx9.meta_levels[level].offset; in vi_dcc_get_clear_info()
441 clear_size = tex->surface.u.gfx9.meta_levels[level].size; in vi_dcc_get_clear_info()
507 assert(tex->surface.u.gfx9.swizzle_mode >= 4); in si_set_optimal_micro_tile_mode()
517 assert(tex->surface.u.gfx9.swizzle_mode % 4 != 0); in si_set_optimal_micro_tile_mode()
521 tex->surface.u.gfx9.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
522 tex->surface.u.gfx9.swizzle_mode += 2; /* D */ in si_set_optimal_micro_tile_mode()
525 tex->surface.u.gfx9.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
526 tex->surface.u.gfx9.swizzle_mode += 1; /* S */ in si_set_optimal_micro_tile_mode()
529 tex->surface.u.gfx9.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
530 tex->surface.u.gfx9 in si_set_optimal_micro_tile_mode()
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H A Dradeon_vce.c226 pitch = align(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe, 256); in si_vce_frame_offset()
227 vpitch = align(enc->luma->u.gfx9.surf_height, 16); in si_vce_frame_offset()
458 align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) * in si_vce_create_encoder()
459 align(tmp_surf->u.gfx9.surf_height, 32); in si_vce_create_encoder()
H A Dradeon_vce_52.c198 RVCE_CS(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe); // encRefPicLumaPitch in create()
199 RVCE_CS(enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe); // encRefPicChromaPitch in create()
200 RVCE_CS(align(enc->luma->u.gfx9.surf_height, 16) / 8); // encRefYHeightInQw in create()
274 enc->luma->u.gfx9.surf_offset); // inputPictureLumaAddressHi/Lo in encode()
276 enc->chroma->u.gfx9.surf_offset); // inputPictureChromaAddressHi/Lo in encode()
277 RVCE_CS(align(enc->luma->u.gfx9.surf_height, 16)); // encInputFrameYPitch in encode()
278 RVCE_CS(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe); // encInputPicLumaPitch in encode()
279 RVCE_CS(enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe); // encInputPicChromaPitch in encode()
H A Dsi_texture.c138 pitch = tex->surface.u.gfx9.pitch[level]; in si_texture_get_offset()
140 pitch = tex->surface.u.gfx9.surf_pitch; in si_texture_get_offset()
144 *layer_stride = tex->surface.u.gfx9.surf_slice_size; in si_texture_get_offset()
151 return tex->surface.u.gfx9.surf_offset + box->z * tex->surface.u.gfx9.surf_slice_size + in si_texture_get_offset()
152 tex->surface.u.gfx9.offset[level] + in si_texture_get_offset()
303 surface->u.gfx9.swizzle_mode = ADDR_SW_64KB_R_X; in si_init_surface()
608 uint64_t level_offset = tex->surface.is_linear ? tex->surface.u.gfx9.offset[level] : 0; in si_resource_get_param()
756 slice_size = tex->surface.u.gfx9.surf_slice_size; in si_texture_get_handle()
1135 tex->surface.u.gfx9 in si_texture_create_object()
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H A Dradeon_vcn_dec_jpeg.c47 dec->jpg.dt_luma_top_offset = luma->surface.u.gfx9.surf_offset; in radeon_jpeg_get_decode_param()
49 dec->jpg.dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset; in radeon_jpeg_get_decode_param()
50 dec->jpg.dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w; in radeon_jpeg_get_decode_param()
H A Dradeon_uvd_enc_1_1.c764 enc->enc_pic.ctx_buf.rec_luma_pitch = enc->luma->u.gfx9.surf_pitch * enc->luma->bpe; in radeon_uvd_enc_ctx()
765 enc->enc_pic.ctx_buf.rec_chroma_pitch = enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe; in radeon_uvd_enc_ctx()
883 enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch * enc->luma->bpe; in radeon_uvd_enc_encode_params_hevc()
885 enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe; in radeon_uvd_enc_encode_params_hevc()
904 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset); in radeon_uvd_enc_encode_params_hevc()
905 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset); in radeon_uvd_enc_encode_params_hevc()
H A Dsi_state.c2178 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) { in si_tex_dim()
2631 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(tex->surface.u.gfx9.color.dcc.max_compressed_block_size) | in si_initialize_color_surface()
2633 S_028C78_INDEPENDENT_64B_BLOCKS(tex->surface.u.gfx9.color.dcc.independent_64B_blocks); in si_initialize_color_surface()
2635 surf->cb_dcc_control |= S_028C78_INDEPENDENT_128B_BLOCKS_GFX11(tex->surface.u.gfx9.color.dcc.independent_128B_blocks); in si_initialize_color_surface()
2637 surf->cb_dcc_control |= S_028C78_INDEPENDENT_128B_BLOCKS_GFX10(tex->surface.u.gfx9.color.dcc.independent_128B_blocks); in si_initialize_color_surface()
2670 S_028EE0_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type) | in si_initialize_color_surface()
2675 S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type); in si_initialize_color_surface()
2719 assert(tex->surface.u.gfx9.surf_offset == 0); in si_init_depth_surface()
2721 surf->db_stencil_base = (tex->buffer.gpu_address + tex->surface.u.gfx9.zs.stencil_offset) >> 8; in si_init_depth_surface()
2724 S_028038_SW_MODE(tex->surface.u.gfx9 in si_init_depth_surface()
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H A Dsi_descriptors.c305 va += tex->surface.u.gfx9.zs.stencil_offset; in si_set_mutable_tex_desc_fields()
307 va += tex->surface.u.gfx9.surf_offset; in si_set_mutable_tex_desc_fields()
347 state[3] |= S_00A00C_SW_MODE(tex->surface.u.gfx9.zs.stencil_swizzle_mode); in si_set_mutable_tex_desc_fields()
349 state[3] |= S_00A00C_SW_MODE(tex->surface.u.gfx9.swizzle_mode); in si_set_mutable_tex_desc_fields()
359 meta = tex->surface.u.gfx9.color.dcc; in si_set_mutable_tex_desc_fields()
383 state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.zs.stencil_swizzle_mode); in si_set_mutable_tex_desc_fields()
384 state[4] |= S_008F20_PITCH(tex->surface.u.gfx9.zs.stencil_epitch); in si_set_mutable_tex_desc_fields()
386 uint16_t epitch = tex->surface.u.gfx9.epitch; in si_set_mutable_tex_desc_fields()
396 state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.swizzle_mode); in si_set_mutable_tex_desc_fields()
409 meta = tex->surface.u.gfx9 in si_set_mutable_tex_desc_fields()
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H A Dradeon_uvd_enc.c327 : align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) * in radeon_uvd_create_encoder()
328 align(tmp_surf->u.gfx9.surf_height, 32); in radeon_uvd_create_encoder()
/third_party/mesa3d/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_bo.c893 tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, md->u.gfx9.swizzle_mode); in radv_amdgpu_winsys_bo_set_metadata()
894 tiling_flags |= AMDGPU_TILING_SET(DCC_OFFSET_256B, md->u.gfx9.dcc_offset_256b); in radv_amdgpu_winsys_bo_set_metadata()
895 tiling_flags |= AMDGPU_TILING_SET(DCC_PITCH_MAX, md->u.gfx9.dcc_pitch_max); in radv_amdgpu_winsys_bo_set_metadata()
896 tiling_flags |= AMDGPU_TILING_SET(DCC_INDEPENDENT_64B, md->u.gfx9.dcc_independent_64b_blocks); in radv_amdgpu_winsys_bo_set_metadata()
898 AMDGPU_TILING_SET(DCC_INDEPENDENT_128B, md->u.gfx9.dcc_independent_128b_blocks); in radv_amdgpu_winsys_bo_set_metadata()
900 AMDGPU_TILING_SET(DCC_MAX_COMPRESSED_BLOCK_SIZE, md->u.gfx9.dcc_max_compressed_block_size); in radv_amdgpu_winsys_bo_set_metadata()
901 tiling_flags |= AMDGPU_TILING_SET(SCANOUT, md->u.gfx9.scanout); in radv_amdgpu_winsys_bo_set_metadata()
947 md->u.gfx9.swizzle_mode = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); in radv_amdgpu_winsys_bo_get_metadata()
948 md->u.gfx9.scanout = AMDGPU_TILING_GET(tiling_flags, SCANOUT); in radv_amdgpu_winsys_bo_get_metadata()
/third_party/mesa3d/src/amd/addrlib/src/gfx9/
H A Dgfx9addrlib.cpp365 pOut->equation.gfx9.num_bits = Min(32u, eq->getsize()); in HwlComputeCmaskInfo()
367 for (unsigned b = 0; b < pOut->equation.gfx9.num_bits; b++) { in HwlComputeCmaskInfo()
373 pOut->equation.gfx9.bit[b].coord[c].dim = coord.getdim(); in HwlComputeCmaskInfo()
374 pOut->equation.gfx9.bit[b].coord[c].ord = coord.getord(); in HwlComputeCmaskInfo()
377 pOut->equation.gfx9.bit[b].coord[c].dim = 5; /* meaning invalid */ in HwlComputeCmaskInfo()
381 for (int b = pOut->equation.gfx9.num_bits - 1; b >= 1; b--) { in HwlComputeCmaskInfo()
388 pOut->equation.gfx9.num_bits = b; in HwlComputeCmaskInfo()
393 pOut->equation.gfx9.numPipeBits = GetPipeLog2ForMetaAddressing(pIn->cMaskFlags.pipeAligned, in HwlComputeCmaskInfo()
730 pOut->equation.gfx9.num_bits = Min(32u, eq->getsize()); in HwlComputeDccInfo()
732 for (unsigned b = 0; b < pOut->equation.gfx9 in HwlComputeDccInfo()
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