| /third_party/vixl/test/aarch64/ |
| H A D | test-disasm-fp-aarch64.cc | 147 COMPARE(fnmul(h4, h5, h6), "fnmul h4, h5, h6"); in TEST()
148 COMPARE(fnmul(s7, s8, s9), "fnmul s7, s8, s9"); in TEST()
149 COMPARE(fnmul(d10, d11, d12), "fnmul d10, d11, d12"); in TEST()
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| H A D | test-cpu-features-aarch64.cc | 633 TEST_FP(fnmul_0, fnmul(d0, d1, d2))
634 TEST_FP(fnmul_1, fnmul(s0, s1, s2))
3498 TEST_FP_FPHALF(fnmul_0, fnmul(h0, h1, h2))
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| H A D | test-simulator-aarch64.cc | 2916 DEFINE_TEST_FP_FP16(fnmul, 2Op, Basic)
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| H A D | test-trace-aarch64.cc | 562 __ fnmul(d31, d19, d1); in GenerateTestSequenceFP()
563 __ fnmul(s18, s3, s17); in GenerateTestSequenceFP()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1637 void fnmul(const VRegister& vd, const VRegister& vn, const VRegister& vm);
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| H A D | macro-assembler-arm64.h | 385 V(fnmul, Fnmul) \
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| H A D | assembler-arm64.cc | 2686 void Assembler::fnmul(const VRegister& vd, const VRegister& vn, in fnmul() function in v8::internal::Assembler
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 2096 LogicVRegister fnmul(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 3236 fnmul(vform, rd, rn, rm);
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| H A D | simulator-logic-arm64.cc | 3277 LogicVRegister Simulator::fnmul(VectorFormat vform, LogicVRegister dst, in fnmul() function in v8::internal::Simulator
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| /third_party/vixl/src/aarch64/ |
| H A D | simulator-aarch64.h | 4560 LogicVRegister fnmul(VectorFormat vform,
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| H A D | assembler-aarch64.h | 2282 void fnmul(const VRegister& vd, const VRegister& vn, const VRegister& vm);
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| H A D | assembler-aarch64.cc | 3445 void Assembler::fnmul(const VRegister& vd,
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| H A D | logic-aarch64.cc | 5036 LogicVRegister Simulator::fnmul(VectorFormat vform,
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| H A D | macro-assembler-aarch64.h | 1706 fnmul(vd, vn, vm); in Fnmul()
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| H A D | simulator-aarch64.cc | 6514 fnmul(vform, rd, rn, rm); in Simulator()
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