| /third_party/ffmpeg/libavcodec/aarch64/ |
| H A D | synth_filter_neon.S | 41 fmls v4.4s, v24.4s, v28.4s
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| H A D | aacpsdsp_neon.S | 137 fmls v0.4S, v3.4S, v18.4S
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| H A D | mpegaudiodsp_neon.S | 223 fmls \d\().4s, \s1\().4s, \s2\().4s
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| /third_party/ffmpeg/libavutil/aarch64/ |
| H A D | float_dsp_neon.S | 127 fmls v16.4S, v4.4S, v2.4S // s0 * wj_r - s1_r * wi
134 fmls v16.4S, v4.4S, v2.4S // s0 * wj_r - s1_r * wi
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| /third_party/vixl/test/aarch64/ |
| H A D | test-api-movprfx-aarch64.cc | 472 __ fmls(z7.VnH(), z11.VnH(), z7.VnH(), 4); in TEST()
475 __ fmls(z3.VnS(), z10.VnS(), z3.VnS(), 3); in TEST()
478 __ fmls(z5.VnD(), z16.VnD(), z5.VnD(), 1); in TEST()
481 __ fmls(z31.VnD(), z31.VnD(), z8.VnD(), 1); in TEST()
484 __ fmls(z5.VnH(), p3.Merging(), z5.VnH(), z2.VnH()); in TEST()
487 __ fmls(z22.VnS(), p3.Merging(), z21.VnS(), z22.VnS()); in TEST()
490 __ fmls(z17.VnH(), z17.VnH(), z2.VnH(), 4); in TEST()
493 __ fmls(z28.VnS(), z28.VnS(), z0.VnS(), 3); in TEST()
976 __ fmls(z15.VnH(), p1.Merging(), z28.VnH(), z20.VnH()); in TEST()
1308 __ fmls(z1 in TEST()
[all...] |
| H A D | test-cpu-features-aarch64.cc | 3289 TEST_FP_NEON(fmls_0, fmls(v0.V2S(), v1.V2S(), v2.S(), 3))
3290 TEST_FP_NEON(fmls_1, fmls(v0.V4S(), v1.V4S(), v2.S(), 1))
3291 TEST_FP_NEON(fmls_2, fmls(v0.V2D(), v1.V2D(), v2.D(), 1))
3292 TEST_FP_NEON(fmls_3, fmls(s0, s1, v2.S(), 3))
3293 TEST_FP_NEON(fmls_4, fmls(d0, d1, v2.D(), 0))
3294 TEST_FP_NEON(fmls_5, fmls(v0.V2S(), v1.V2S(), v2.V2S()))
3295 TEST_FP_NEON(fmls_6, fmls(v0.V4S(), v1.V4S(), v2.V4S()))
3681 TEST_FP_NEON_NEONHALF(fmls_0, fmls(v0.V4H(), v1.V4H(), v2.H(), 0))
3682 TEST_FP_NEON_NEONHALF(fmls_1, fmls(v0.V8H(), v1.V8H(), v2.H(), 0))
3683 TEST_FP_NEON_NEONHALF(fmls_2, fmls(h
[all...] |
| H A D | test-trace-aarch64.cc | 2667 __ fmls(d27, d30, v6.D(), 0); in GenerateTestSequenceNEONFP()
2668 __ fmls(s21, s16, v2.S(), 0); in GenerateTestSequenceNEONFP()
2669 __ fmls(v5.V2D(), v19.V2D(), v21.V2D()); in GenerateTestSequenceNEONFP()
2670 __ fmls(v18.V2D(), v30.V2D(), v12.D(), 0); in GenerateTestSequenceNEONFP()
2671 __ fmls(v5.V2S(), v16.V2S(), v7.V2S()); in GenerateTestSequenceNEONFP()
2672 __ fmls(v3.V2S(), v18.V2S(), v11.S(), 1); in GenerateTestSequenceNEONFP()
2673 __ fmls(v27.V4S(), v5.V4S(), v30.V4S()); in GenerateTestSequenceNEONFP()
2674 __ fmls(v26.V4S(), v20.V4S(), v4.S(), 3); in GenerateTestSequenceNEONFP()
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| H A D | test-disasm-sve-aarch64.cc | 1576 COMPARE(fmls(z20.VnH(), p6.Merging(), z28.VnH(), z0.VnH()), in TEST()
1577 "fmls z20.h, p6/m, z28.h, z0.h"); in TEST()
1578 COMPARE(fmls(z20.VnS(), p6.Merging(), z28.VnS(), z0.VnS()), in TEST()
1579 "fmls z20.s, p6/m, z28.s, z0.s"); in TEST()
1580 COMPARE(fmls(z20.VnD(), p6.Merging(), z28.VnD(), z0.VnD()), in TEST()
1581 "fmls z20.d, p6/m, z28.d, z0.d"); in TEST()
1639 "fmls z0.d, p1/m, z2.d, z4.d"); in TEST()
1644 "fmls z31.h, p3/m, z6.h, z4.h\n" in TEST()
1648 "fmls z5.d, p4/m, z7.d, z8.d"); in TEST()
1700 "fmls z in TEST()
[all...] |
| H A D | test-simulator-aarch64.cc | 4631 DEFINE_TEST_NEON_3SAME_FP(fmls, Basic)
4985 DEFINE_TEST_NEON_FP_BYELEMENT(fmls, Basic, Basic, Basic)
5004 DEFINE_TEST_NEON_FP_BYELEMENT_SCALAR(fmls, Basic, Basic, Basic)
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-logic-arm64.cc | 3505 LogicVRegister Simulator::fmls(VectorFormat vform, LogicVRegister dst, in fmls() function in v8::internal::Simulator
3519 LogicVRegister Simulator::fmls(VectorFormat vform, LogicVRegister dst, in fmls() function in v8::internal::Simulator
3523 fmls<float>(vform, dst, src1, src2); in fmls()
3526 fmls<double>(vform, dst, src1, src2); in fmls()
3697 LogicVRegister Simulator::fmls(VectorFormat vform, LogicVRegister dst, in fmls() function in v8::internal::Simulator
3704 fmls<float>(vform, dst, src1, index_reg); in fmls()
3708 fmls<double>(vform, dst, src1, index_reg); in fmls()
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| H A D | simulator-arm64.h | 1624 LogicVRegister fmls(VectorFormat vform, LogicVRegister dst,
2092 LogicVRegister fmls(VectorFormat vform, LogicVRegister dst,
2094 LogicVRegister fmls(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 4242 fmls(vf, rd, rn, rm);
4778 Op = &Simulator::fmls;
5660 Op = &Simulator::fmls;
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| /third_party/vixl/src/aarch64/ |
| H A D | logic-aarch64.cc | 5260 LogicVRegister Simulator::fmls(VectorFormat vform,
5277 LogicVRegister Simulator::fmls(VectorFormat vform,
5283 fmls<SimFloat16>(vform, dst, srca, src1, src2);
5285 fmls<float>(vform, dst, srca, src1, src2);
5288 fmls<double>(vform, dst, srca, src1, src2);
5743 LogicVRegister Simulator::fmls(VectorFormat vform,
5752 fmls<SimFloat16>(vform, dst, dst, src1, index_reg);
5755 fmls<float>(vform, dst, dst, src1, index_reg);
5759 fmls<double>(vform, dst, dst, src1, index_reg);
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| H A D | macro-assembler-sve-aarch64.cc | 1857 V(Fmls, fmls, FourRegOneImmDestructiveHelper) \
1978 // zda = (-)zda + ((-)zn * zm) for fmla, fmls, fnmla and fnmls. in FPMulAddHelper()
2013 // zd = (-)za + ((-)zn * zm) for fmla, fmls, fnmla and fnmls. in FPMulAddHelper()
2048 &Assembler::fmls, in Fmls()
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| H A D | simulator-aarch64.cc | 7396 fmls(vf, rd, rd, rn, rm); in Simulator()
7638 fmls(vf, rd, rd, rn, rm); in Simulator()
8065 fmls(vform, rd, rn, rm, index); in Simulator()
9217 Op = &Simulator::fmls; in Simulator()
10605 fmls(vform, result, result, zn, zm); in Simulator()
10609 fmls(vform, result, zd, zn, zm); in Simulator()
10633 fmls(vform, result, result, zd, zm); in Simulator()
10637 fmls(vform, result, za, zd, zm); in Simulator()
10682 fmls(vform, zd, zd, zn, temp); in Simulator()
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| H A D | simulator-aarch64.h | 3526 LogicVRegister fmls(VectorFormat vform,
4550 LogicVRegister fmls(VectorFormat vform,
4555 LogicVRegister fmls(VectorFormat vform,
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| H A D | assembler-aarch64.h | 3505 void fmls(const VRegister& vd, const VRegister& vn, const VRegister& vm);
3547 void fmls(const VRegister& vd,
4356 void fmls(const ZRegister& zda,
4363 void fmls(const ZRegister& zda,
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| H A D | assembler-aarch64.cc | 4235 V(fmls, NEON_FMLS, 0, 0) \
4787 V(fmls, NEON_FMLS_byelement, NEON_FMLS_H_byelement) \
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| H A D | assembler-sve-aarch64.cc | 1433 void Assembler::fmls(const ZRegister& zda, in fmls() function in vixl::aarch64::Assembler
1626 void Assembler::fmls(const ZRegister& zda, in fmls() function in vixl::aarch64::Assembler
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| H A D | macro-assembler-aarch64.h | 2880 V(fmls, Fmls) \
3110 V(fmls, Fmls) \
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1569 void fmls(const VRegister& vd, const VRegister& vn, const VRegister& vm);
1589 void fmls(const VRegister& vd, const VRegister& vn, const VRegister& vm,
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| H A D | macro-assembler-arm64.h | 216 V(fmls, Fmls) \
383 V(fmls, Fmls) \
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| H A D | assembler-arm64.cc | 3135 V(fmls, NEON_FMLS, 0) \
3344 V(fmls, NEON_FMLS_byelement) \
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