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/third_party/ffmpeg/libavcodec/aarch64/
H A Dopusdsp_neon.S49 fmla v0.4s, v5.4s, v1.s[0]
52 fmla v0.4s, v6.4s, v1.s[1]
53 fmla v3.4s, v6.4s, v2.s[1]
55 fmla v0.4s, v7.4s, v1.s[2]
56 fmla v3.4s, v5.4s, v2.s[0]
61 fmla v2.4s, v4.4s, v1.s[3]
95 fmla v3.4s, v7.4s, v2.4s
99 fmla v4.4s, v5.4s, v0.4s
H A Daacpsdsp_neon.S61 fmla v2.4S, v3.4S, v5.4S
89 fmla v4.4S, v3.4S, v17.4S
94 fmla v4.4S, v2.4S, v18.4S
95 fmla v4.4S, v3.4S, v19.4S
138 fmla v1.4S, v3.4S, v19.4S
139 fmla v0.4S, v4.4S, v20.4S
140 fmla v1.4S, v4.4S, v21.4S
H A Dsynth_filter_neon.S36 fmla v5.4s, v25.4s, v29.4s
40 fmla v6.4s, v26.4s, v30.4s
42 fmla v7.4s, v27.4s, v31.4s
H A Dsbrdsp_neon.S67 fmla v0.4S, v1.4S, v1.4S
240 fmla v1.2S, v4.2S, v4.2S
241 fmla v2.4S, v5.4S, v4.S[0]
242 fmla v3.4S, v5.4S, v4.S[1]
288 fmla v6.4S, v1.4S, v3.4S
289 fmla v2.4S, v5.4S, v4.4S
H A Dfft_neon.S187 fmla v25.4s, v7.4s, v23.s[3] // {t1a,t2a,t5a,t6a}
211 fmla v26.4s, v6.4s, v23.s[2] // {t1,t2,t5,t6}
212 fmla v27.4s, v7.4s, v23.s[1] // {t1a,t2a,t5a,t6a}
275 fmla v25.4s, v7.4s, v5.s[0] // {t1a,t2a,t5a,t6a}
311 fmla v26.4s, v6.4s, v5.s[1] // {t1,t2,t5,t6}
312 fmla v27.4s, v7.4s, v5.s[0] // {t1a,t2a,t5a,t6a}
H A Dmpegaudiodsp_neon.S220 fmla \d\().4s, \s1\().4s, \s2\().4s
/third_party/ffmpeg/libavutil/aarch64/
H A Dfloat_dsp_neon.S49 fmla v16.4S, v4.4S, v0.S[0]
50 fmla v17.4S, v5.4S, v0.S[0]
51 fmla v18.4S, v6.4S, v0.S[0]
52 fmla v19.4S, v7.4S, v0.S[0]
124 fmla v17.4S, v1.4S, v3.4S // (s0 * wi)_rev + s1 * wj
145 fmla v4.4S, v0.4S, v2.4S
146 fmla v5.4S, v1.4S, v3.4S
197 fmla v2.4S, v0.4S, v1.4S
/third_party/ffmpeg/libswresample/aarch64/
H A Dresample.S27 fmla v0.4S, v1.4S, v2.4S // accumulator += src[0..3] * filter[0..3]
42 fmla v0.4S, v1.4S, v2.4S // accumulator += src[0..3] * filter[0..3]
43 fmla v0.4S, v3.4S, v4.4S // accumulator += src[4..7] * filter[4..7]
/third_party/ffmpeg/libavresample/aarch64/
H A Dresample_neon.S127 fmla \d\().2d, \r0\().2d, \r1\().2d
160 fmla \d\().4s, \r0\().4s, \r1\().4s
/third_party/vixl/test/aarch64/
H A Dtest-api-movprfx-aarch64.cc448 __ fmla(z4.VnH(), z24.VnH(), z4.VnH(), 7); in TEST()
451 __ fmla(z4.VnS(), z24.VnS(), z4.VnS(), 3); in TEST()
454 __ fmla(z5.VnD(), z28.VnD(), z5.VnD(), 1); in TEST()
457 __ fmla(z24.VnD(), z24.VnD(), z2.VnD(), 1); in TEST()
460 __ fmla(z7.VnH(), p2.Merging(), z7.VnH(), z31.VnH()); in TEST()
463 __ fmla(z25.VnH(), p5.Merging(), z29.VnH(), z25.VnH()); in TEST()
466 __ fmla(z31.VnH(), z31.VnH(), z2.VnH(), 7); in TEST()
469 __ fmla(z15.VnS(), z15.VnS(), z4.VnS(), 3); in TEST()
973 __ fmla(z13.VnD(), p3.Merging(), z12.VnD(), z21.VnD()); in TEST()
1299 __ fmla(z1 in TEST()
[all...]
H A Dtest-cpu-features-aarch64.cc3282 TEST_FP_NEON(fmla_0, fmla(v0.V2S(), v1.V2S(), v2.S(), 3))
3283 TEST_FP_NEON(fmla_1, fmla(v0.V4S(), v1.V4S(), v2.S(), 2))
3284 TEST_FP_NEON(fmla_2, fmla(v0.V2D(), v1.V2D(), v2.D(), 0))
3285 TEST_FP_NEON(fmla_3, fmla(s0, s1, v2.S(), 1))
3286 TEST_FP_NEON(fmla_4, fmla(d0, d1, v2.D(), 0))
3287 TEST_FP_NEON(fmla_5, fmla(v0.V2S(), v1.V2S(), v2.V2S()))
3288 TEST_FP_NEON(fmla_6, fmla(v0.V4S(), v1.V4S(), v2.V4S()))
3676 TEST_FP_NEON_NEONHALF(fmla_0, fmla(v0.V4H(), v1.V4H(), v2.H(), 4))
3677 TEST_FP_NEON_NEONHALF(fmla_1, fmla(v0.V8H(), v1.V8H(), v2.H(), 2))
3678 TEST_FP_NEON_NEONHALF(fmla_2, fmla(h
[all...]
H A Dtest-trace-aarch64.cc2659 __ fmla(d23, d0, v9.D(), 1); in GenerateTestSequenceNEONFP()
2660 __ fmla(s23, s15, v7.S(), 0); in GenerateTestSequenceNEONFP()
2661 __ fmla(v17.V2D(), v11.V2D(), v6.V2D()); in GenerateTestSequenceNEONFP()
2662 __ fmla(v30.V2D(), v30.V2D(), v11.D(), 0); in GenerateTestSequenceNEONFP()
2663 __ fmla(v19.V2S(), v12.V2S(), v6.V2S()); in GenerateTestSequenceNEONFP()
2664 __ fmla(v24.V2S(), v17.V2S(), v9.S(), 0); in GenerateTestSequenceNEONFP()
2665 __ fmla(v16.V4S(), v11.V4S(), v11.V4S()); in GenerateTestSequenceNEONFP()
2666 __ fmla(v27.V4S(), v23.V4S(), v9.S(), 2); in GenerateTestSequenceNEONFP()
H A Dtest-disasm-sve-aarch64.cc1570 COMPARE(fmla(z26.VnH(), p7.Merging(), z19.VnH(), z16.VnH()), in TEST()
1571 "fmla z26.h, p7/m, z19.h, z16.h"); in TEST()
1572 COMPARE(fmla(z26.VnS(), p7.Merging(), z19.VnS(), z16.VnS()), in TEST()
1573 "fmla z26.s, p7/m, z19.s, z16.s"); in TEST()
1574 COMPARE(fmla(z26.VnD(), p7.Merging(), z19.VnD(), z16.VnD()), in TEST()
1575 "fmla z26.d, p7/m, z19.d, z16.d"); in TEST()
1627 "fmla z0.h, p1/m, z2.h, z4.h"); in TEST()
1632 "fmla z31.s, p3/m, z6.s, z4.s\n" in TEST()
1636 "fmla z5.d, p4/m, z7.d, z8.d"); in TEST()
1690 "fmla z in TEST()
[all...]
H A Dtest-simulator-aarch64.cc4622 DEFINE_TEST_NEON_3SAME_FP(fmla, Basic)
4984 DEFINE_TEST_NEON_FP_BYELEMENT(fmla, Basic, Basic, Basic)
5003 DEFINE_TEST_NEON_FP_BYELEMENT_SCALAR(fmla, Basic, Basic, Basic)
/third_party/vixl/src/aarch64/
H A Dlogic-aarch64.cc5225 LogicVRegister Simulator::fmla(VectorFormat vform,
5242 LogicVRegister Simulator::fmla(VectorFormat vform,
5248 fmla<SimFloat16>(vform, dst, srca, src1, src2);
5250 fmla<float>(vform, dst, srca, src1, src2);
5253 fmla<double>(vform, dst, srca, src1, src2);
5721 LogicVRegister Simulator::fmla(VectorFormat vform,
5730 fmla<SimFloat16>(vform, dst, dst, src1, index_reg);
5733 fmla<float>(vform, dst, dst, src1, index_reg);
5737 fmla<double>(vform, dst, dst, src1, index_reg);
6629 fmla<
[all...]
H A Dmacro-assembler-sve-aarch64.cc1856 V(Fmla, fmla, FourRegOneImmDestructiveHelper) \
1978 // zda = (-)zda + ((-)zn * zm) for fmla, fmls, fnmla and fnmls. in FPMulAddHelper()
2013 // zd = (-)za + ((-)zn * zm) for fmla, fmls, fnmla and fnmls. in FPMulAddHelper()
2031 &Assembler::fmla, in Fmla()
H A Dsimulator-aarch64.cc7393 fmla(vf, rd, rd, rn, rm); in Simulator()
7635 fmla(vf, rd, rd, rn, rm); in Simulator()
8061 fmla(vform, rd, rn, rm, index); in Simulator()
9213 Op = &Simulator::fmla; in Simulator()
10600 fmla(vform, result, zd, zn, zm); in Simulator()
10614 fmla(vform, result, result, zn, zm); in Simulator()
10628 fmla(vform, result, za, zd, zm); in Simulator()
10642 fmla(vform, result, result, zd, zm); in Simulator()
10684 fmla(vform, zd, zd, zn, temp); in Simulator()
H A Dsimulator-aarch64.h3511 LogicVRegister fmla(VectorFormat vform,
4539 LogicVRegister fmla(VectorFormat vform,
4544 LogicVRegister fmla(VectorFormat vform,
H A Dassembler-aarch64.h3484 void fmla(const VRegister& vd, const VRegister& vn, const VRegister& vm);
3541 void fmla(const VRegister& vd,
4342 void fmla(const ZRegister& zda,
4349 void fmla(const ZRegister& zda,
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-logic-arm64.cc3478 LogicVRegister Simulator::fmla(VectorFormat vform, LogicVRegister dst, in fmla() function in v8::internal::Simulator
3492 LogicVRegister Simulator::fmla(VectorFormat vform, LogicVRegister dst, in fmla() function in v8::internal::Simulator
3496 fmla<float>(vform, dst, src1, src2); in fmla()
3499 fmla<double>(vform, dst, src1, src2); in fmla()
3681 LogicVRegister Simulator::fmla(VectorFormat vform, LogicVRegister dst, in fmla() function in v8::internal::Simulator
3688 fmla<float>(vform, dst, src1, index_reg); in fmla()
3692 fmla<double>(vform, dst, src1, index_reg); in fmla()
H A Dsimulator-arm64.h1621 LogicVRegister fmla(VectorFormat vform, LogicVRegister dst,
2087 LogicVRegister fmla(VectorFormat vform, LogicVRegister dst,
2089 LogicVRegister fmla(VectorFormat vform, LogicVRegister dst,
H A Dsimulator-arm64.cc4239 fmla(vf, rd, rn, rm);
4775 Op = &Simulator::fmla;
5657 Op = &Simulator::fmla;
/third_party/node/deps/v8/src/codegen/arm64/
H A Dassembler-arm64.h1566 void fmla(const VRegister& vd, const VRegister& vn, const VRegister& vm);
1585 void fmla(const VRegister& vd, const VRegister& vn, const VRegister& vm,
H A Dmacro-assembler-arm64.h215 V(fmla, Fmla) \
382 V(fmla, Fmla) \
H A Dassembler-arm64.cc3134 V(fmla, NEON_FMLA, 0) \
3343 V(fmla, NEON_FMLA_byelement) \

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