| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1206 void fminnmv(const VRegister& vd, const VRegister& vn);
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| H A D | macro-assembler-arm64.h | 276 V(fminnmv, Fminnmv) \
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| H A D | assembler-arm64.cc | 2045 V(fminnmv, NEON_FMINNMV, vd.Is1S()) \
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 2170 LogicVRegister fminnmv(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 4625 fminnmv(vf, rd, rn);
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| H A D | simulator-logic-arm64.cc | 3660 LogicVRegister Simulator::fminnmv(VectorFormat vform, LogicVRegister dst, in fminnmv() function in v8::internal::Simulator
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| /third_party/vixl/src/aarch64/ |
| H A D | assembler-aarch64.h | 3058 void fminnmv(const VRegister& vd, const VRegister& vn);
4335 void fminnmv(const VRegister& vd, const PRegister& pg, const ZRegister& zn);
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| H A D | simulator-aarch64.cc | 7890 fminnmv(vf, rd, rn); in Simulator()
7910 fminnmv(vf, rd, rn); in Simulator()
10540 fn = &Simulator::fminnmv; in Simulator()
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| H A D | simulator-aarch64.h | 4811 LogicVRegister fminnmv(VectorFormat vform,
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| H A D | macro-assembler-aarch64.h | 3022 V(fminnmv, Fminnmv) \
4632 fminnmv(vd, pg, zn); in Fminnmv()
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| H A D | assembler-aarch64.cc | 5391 V(fminnmv, NEON_FMINNMV, NEON_FMINNMV_H) \
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| H A D | assembler-sve-aarch64.cc | 1371 void Assembler::fminnmv(const VRegister& vd, in fminnmv() function in vixl::aarch64::Assembler
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| H A D | logic-aarch64.cc | 5684 LogicVRegister Simulator::fminnmv(VectorFormat vform,
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| /third_party/vixl/test/aarch64/ |
| H A D | test-cpu-features-aarch64.cc | 3269 TEST_FP_NEON(fminnmv_0, fminnmv(s0, v1.V4S()))
3668 TEST_FP_NEON_NEONHALF(fminnmv_0, fminnmv(h0, v1.V4H()))
3669 TEST_FP_NEON_NEONHALF(fminnmv_1, fminnmv(h0, v1.V8H()))
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| H A D | test-simulator-aarch64.cc | 4957 DEFINE_TEST_NEON_ACROSS_FP(fminnmv, Basic)
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| H A D | test-disasm-sve-aarch64.cc | 1551 COMPARE(fminnmv(h20, p6, z21.VnH()), "fminnmv h20, p6, z21.h"); in TEST()
1552 COMPARE(fminnmv(s20, p6, z21.VnS()), "fminnmv s20, p6, z21.s"); in TEST()
1553 COMPARE(fminnmv(d20, p6, z21.VnD()), "fminnmv d20, p6, z21.d"); in TEST()
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| H A D | test-trace-aarch64.cc | 2652 __ fminnmv(s3, v4.V4S()); in GenerateTestSequenceNEONFP()
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